Datasheet Texas Instruments CD4020BPWR — Ficha de datos

FabricanteTexas Instruments
SerieCD4020B
Numero de parteCD4020BPWR
Datasheet Texas Instruments CD4020BPWR

Contador / divisor binario de 14 etapas CMOS Ripple-Carry 16-TSSOP -55 a 125

Hojas de datos

CD4020B, CD4024B, CD4040B TYPES datasheet
PDF, 1.6 Mb, Revisión: D, Archivo publicado: dic 11, 2003
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin16
Package TypePW
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingCM020B
Width (mm)4.4
Length (mm)5
Thickness (mm)1
Pitch (mm)0.65
Max Height (mm)1.2
Mechanical DataDescargar

Paramétricos

Approx. price0.11 | 1ku US$
Bits12
F @ nom voltage(Max)8 MHz
FunctionCounter
ICC @ nom voltage(Max)0.03 mA
IOH(Max)-1.5 mA
IOL(Max)1.5 mA
Operating temperature range-55 to 125 C
Package GroupPDIP|16,SO|16,TSSOP|16
Package size: mm2:W x LSee datasheet (PDIP),16SO: 80 mm2: 7.8 x 10.2 (SO|16),16TSSOP: 22 mm2: 4.4 x 5 (TSSOP|16) PKG
RatingCatalog
Technology FamilyCD4000
TypeBinary
VCC(Max)18 V
VCC(Min)3 V
Voltage(Nom)5,10,15 V
tpd @ nom Voltage(Max)160 ns

Plan ecológico

RoHSObediente
Pb gratis

Notas de aplicación

  • Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics
    PDF, 188 Kb, Archivo publicado: dic 3, 2001
    Both buffered and unbuffered CMOS B-series gates inverters and high-current IC products are available from TI. Each product classification has application advantages in appropriate logic-system designs. Many CMOS suppliers have concentrated on promoting buffered B-series products with applications literature focusing on the attributes and use of the buffered types. This practice has left an imb
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, Archivo publicado: jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, Revisión: C, Archivo publicado: dic 2, 2015

Linea modelo

Clasificación del fabricante

  • Semiconductors > Logic > Specialty logic > Counter/arithmetic/parity function