Datasheet Texas Instruments ADS8365IPAG — Ficha de datos

FabricanteTexas Instruments
SerieADS8365
Numero de parteADS8365IPAG
Datasheet Texas Instruments ADS8365IPAG

16 bits 250kSPS 6-Ch Muestreo simultáneo SAR ADC 64-TQFP -40 a 85

Hojas de datos

16-Bit, 250kSPS 6-Channel Simultaneous Sampling SAR Analog-to-Digital Converters datasheet
PDF, 988 Kb, Revisión: C, Archivo publicado: marzo 27, 2008
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin64
Package TypePAG
Industry STD TermTQFP
JEDEC CodeS-PQFP-G
Package QTY160
CarrierJEDEC TRAY (10+1)
Device MarkingADS8365AI
Width (mm)10
Length (mm)10
Thickness (mm)1
Pitch (mm).5
Max Height (mm)1.2
Mechanical DataDescargar

Paramétricos

# Input Channels6
Analog Voltage AVDD(Max)5.25 V
Analog Voltage AVDD(Min)4.75 V
ArchitectureSAR
Digital Supply(Max)5.5 V
Digital Supply(Min)2.7 V
INL(Max)4 +/-LSB
Input Range(Max)2.6 V
Input Range(Min)-2.6 V
Input TypePseudo-Differential
Integrated FeaturesN/A
InterfaceParallel
Multi-Channel ConfigurationSimultaneous Sampling
Operating Temperature Range-40 to 85 C
Package GroupTQFP
Package Size: mm2:W x L64TQFP: 144 mm2: 12 x 12(TQFP) PKG
Power Consumption(Typ)190 mW
RatingCatalog
Reference ModeExt,Int
Resolution16 Bits
SINAD87 dB
SNR88 dB
Sample Rate (max)250kSPS SPS
Sample Rate(Max)0.25 MSPS
THD(Typ)-94 dB

Plan ecológico

RoHSObediente

Kits de diseño y Módulos de evaluación

  • Evaluation Modules & Boards: ADS8365M-EVM
    ADS8365M Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)

Notas de aplicación

  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, Revisión: A, Archivo publicado: nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, Archivo publicado: marzo 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

Linea modelo

Serie: ADS8365 (3)

Clasificación del fabricante

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)