Datasheet Texas Instruments SN74ALVCH244 — Ficha de datos

FabricanteTexas Instruments
SerieSN74ALVCH244
Datasheet Texas Instruments SN74ALVCH244

Octal Buffer / Driver con salidas de 3 estados

Hojas de datos

SN74ALVCH244 datasheet
PDF, 835 Kb, Revisión: F, Archivo publicado: agosto 20, 2004
Extracto del documento

Precios

Estado

SN74ALVCH244DGVRSN74ALVCH244DWSN74ALVCH244DWRSN74ALVCH244PWSN74ALVCH244PWLESN74ALVCH244PWRSN74ALVCH244PWRE4
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNoNoNoNo

Embalaje

SN74ALVCH244DGVRSN74ALVCH244DWSN74ALVCH244DWRSN74ALVCH244PWSN74ALVCH244PWLESN74ALVCH244PWRSN74ALVCH244PWRE4
N1234567
Pin20202020202020
Package TypeDGVDWDWPWPWPWPW
Industry STD TermTVSOPSOICSOICTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY20002520007020002000
CarrierLARGE T&RTUBELARGE T&RTUBELARGE T&RLARGE T&R
Device MarkingVB244ALVCH244ALVCH244VB244VB244VB244
Width (mm)4.47.57.54.44.44.44.4
Length (mm)512.812.86.56.56.56.5
Thickness (mm)1.052.352.351111
Pitch (mm).41.271.27.65.65.65.65
Max Height (mm)1.22.652.651.21.21.21.2
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsSN74ALVCH244DGVR
SN74ALVCH244DGVR
SN74ALVCH244DW
SN74ALVCH244DW
SN74ALVCH244DWR
SN74ALVCH244DWR
SN74ALVCH244PW
SN74ALVCH244PW
SN74ALVCH244PWLE
SN74ALVCH244PWLE
SN74ALVCH244PWR
SN74ALVCH244PWR
SN74ALVCH244PWRE4
SN74ALVCH244PWRE4
Approx. Price (US$)0.20 | 1ku
Bits888888
Bits(#)8
F @ Nom Voltage(Max), Mhz100100100100100100
F @ Nom Voltage(Max)(Mhz)100
ICC @ Nom Voltage(Max), mA0.010.010.010.010.010.01
ICC @ Nom Voltage(Max)(mA)0.01
Input TypeLVTTL
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85
Output Drive (IOL/IOH)(Max), mA-24/24-24/24-24/24-24/24-24/24-24/24
Output Drive (IOL/IOH)(Max)(mA)-24/24
Output TypeLVTTL
Package GroupTVSOPSOICSOICTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG20TVSOP: 32 mm2: 6.4 x 5(TVSOP)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
Package Size: mm2:W x L (PKG)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNo
Technology FamilyALVCALVCALVCALVCALVCALVCALVC
VCC(Max), V3.63.63.63.63.63.6
VCC(Max)(V)3.6
VCC(Min), V1.651.651.651.651.651.65
VCC(Min)(V)1.65
Voltage(Nom), V1.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.3
Voltage(Nom)(V)1.8
2.5
2.7
3.3
tpd @ Nom Voltage(Max), ns3.1,2.83.1,2.83.1,2.83.1,2.83.1,2.83.1,2.8
tpd @ Nom Voltage(Max)(ns)3.1
2.8

Plan ecológico

SN74ALVCH244DGVRSN74ALVCH244DWSN74ALVCH244DWRSN74ALVCH244PWSN74ALVCH244PWLESN74ALVCH244PWRSN74ALVCH244PWRE4
RoHSObedienteObedienteObedienteObedienteDesobedienteObedienteObediente
Pb gratisNo

Notas de aplicación

  • TI SN74ALVC16835 Component Specification Analysis for PC100
    PDF, 43 Kb, Archivo publicado: agosto 3, 1998
    The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
  • Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
    PDF, 96 Kb, Revisión: A, Archivo publicado: mayo 13, 1998
    Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
  • Bus-Hold Circuit
    PDF, 418 Kb, Archivo publicado: feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revisión: B, Archivo publicado: mayo 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
    PDF, 154 Kb, Revisión: A, Archivo publicado: sept 8, 1999
    In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families

Linea modelo

Clasificación del fabricante

  • Semiconductors> Logic> Buffer/Driver/Transceiver> Non-Inverting Buffer/Driver