Datasheet AD9059 (Analog Devices) - 8

AD9059 THEORY OF OPERATION
Figure 3 shows typical connections for high performance dc The AD9059 combines Analog Devices’ proprietary MagAmp biasing using the ADC’s internal voltage reference. All compo- gray code conversion circuitry with flash converter technology to nents may be powered from a single 5 V supply (analog input provide dual high performance 8-bit ADCs in a single low cost signals are referenced to ground). monolithic device. The design architecture ensures low power, high speed, and 8-bit accuracy.
1k
⍀ The AD9059 provides two linked ADC channels that are clocked
+5V
from a single ENCODE input (see Functional Block Diagram).
+5V 1k
⍀ The two ADC channels simultaneously sample the analog inputs
VIN AD8041 A 1
(AINA and AINB) and provide noninterleaved parallel digital
AINA
outputs (D0A–D7A and D0B–D7B). The voltage reference
10k
⍀
3 VREF
(VREF) is internally connected to both ADCs so channel gains and offsets will track if external reference control is desired.
10k
⍀
0.1µF AD9059
The analog input signal is buffered at the input of each ADC
5V
channel and applied to a high speed track-and-hold. The track-
AD8041
and-hold circuit holds the analog input value during the
1k
⍀
28 AINB V I N B
conversion process (beginning with the rising edge of the
(–0.5V TO +0.5V) 1k
⍀ ENCODE command). The track-and-hold’s output signal passes through the gray code and flash conversion stages to generate coarse and fine digital representations of the held analog input Figure 3. DC-Coupled AD9059 (VIN Inverted) level. Decode logic combines the multistage data and aligns the
Voltage Reference
8-bit word for strobed outputs on the rising edge of the ENCODE A stable and accurate 2.5 V voltage reference is built into the command. The MagAmp/Flash architecture of the AD9059 AD9059 (VREF). The reference output is used to set the ADC results in three pipeline delays for the output data. gain/offset and can provide dc bias for the analog input signals. The internal reference is tied to the ADC circuitry through an
USING THE AD9059
800 Ω internal impedance and is capable of providing 300 µA
Analog Inputs
The AD9059 provides independent single-ended high impedance external drive current (for dc biasing the analog input or other (150 kΩ) analog inputs for the dual ADCs. Each input requires a user circuitry). dc bias current of 6 µA (typical) centered near 2.5 V (±10%). The Some applications may require greater accuracy, improved dc bias may be provided by the user or may be derived from the temperature performance, or gain adjustments that cannot be ADC’s internal voltage reference. Figure 2 shows a low cost dc obtained using the internal reference. An external voltage may bias implementation that allows the user to capacitively couple be applied to the VREF pin to overdrive the internal voltage ac signals directly into the ADC without additional active cir- reference for gain adjustment of up to ± 10% (the VREF pin is cuitry. For best dynamic performance, the VREF pin should internally tied directly to the ADC circuitry). ADC gain and be decoupled to ground with a 0.1 µF capacitor (to minimize offset will vary simultaneously with external reference adjust- modulation of the reference voltage), and the bias resistor should ment with a 1:1 ratio (a 2% or 50 mV adjustment to the 2.5 V be approximately 1 kΩ. reference varies ADC gain by 2% and ADC offset by 50 mV). Theoretical input voltage range versus reference input voltage
5V
may be calculated using the following equations.
0.1µF
V ( p − p) = VREF . 2 5 RANGE
VIN 1 A AINA
V = VREF
(1V p-p)
MIDSCALE
1k
⍀
AD9059
V − − = VREF + V 2 TOP OF RANGE RANGE V − − = VREF – V 2
EXTERNAL V
BOTTOM OF RANGE RANGE
REF 3 VREF (OPTIONAL) 0.1µF
The external reference should have a 1 mA minimum sink/
1k
⍀ source current capability to ensure complete overdrive of the
VIN 28 AINB
internal voltage reference.
B (1V p-p) 0.1µF
Figure 2. Capacity Coupled AD9059 REV. A –7– Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION SPECIFICATIONS EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics THEORY OF OPERATION USING THE AD9059 Analog Inputs Voltage Reference Digital Logic (5 V/3 V Systems) Timing Power Dissipation Applications Evaluation Board OUTLINE DIMENSIONS Revision History