Datasheet MCP621S, MCP621S, MCP622, MCP623, MCP624, MCP625, MCP629 (Microchip) - 3

FabricanteMicrochip
DescripciónThe MCP62x family of operational amplifiers feature low offset
Páginas / Página62 / 3 — MCP621/1S/2/3/4/5/9. 1.0. ELECTRICAL CHARACTERISTICS. 1.1. Absolute …
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MCP621/1S/2/3/4/5/9. 1.0. ELECTRICAL CHARACTERISTICS. 1.1. Absolute Maximum Ratings †. † Notice:

MCP621/1S/2/3/4/5/9 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † † Notice:

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MCP621
MCP621S
MCP622
MCP623
MCP624
MCP625
MCP629

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MCP621/1S/2/3/4/5/9 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † † Notice:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to VDD – VSS ...6.5V the device. This is a stress rating only and functional Current at Input Pins ..±2 mA operation of the device at those or any other Analog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD + 1.0V conditions above those indicated in the operational All Other Inputs and Outputs ... VSS – 0.3V to VDD + 0.3V listings of this specification is not implied. Exposure to Output Short Circuit Current .. Continuous maximum rating conditions for extended periods may Current at Output and Supply Pins ..±150 mA affect device reliability. Storage Temperature ...-65°C to +150°C
††
See
Section 4.2.2, Input Voltage and Current
Max. Junction Temperature .. +150°C
Limits
. ESD protection on all pins (HBM, MM)  1 kV, 200V
1.2 Specifications TABLE 1-1: DC ELECTRICAL SPECIFICATIONS Electrical Characteristics:
Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3, VOUT  VDD/2, VL = VDD/2, RL = 2 k to VL and CAL/CS = VSS (refer to Figure 1-2).
Parameters Sym. Min. Typ. Max. Units Conditions Input Offset
Input Offset Voltage VOS -200 — +200 µV After calibration
(Note 1 )
Input Offset Voltage Trim Step VOSTRM — 37 200 µV
(Note 2)
Size Input Offset Voltage Drift VOS/TA — ±2.0 — µV/°C TA = -40°C to +125°C Power Supply Rejection Ratio PSRR 61 76 — dB
Input Current and Impedance
Input Bias Current IB — 5 — pA Across Temperature IB — 100 — pA TA = +85°C Across Temperature IB — 1700 5,000 pA TA = +125°C Input Offset Current IOS — ±10 — pA Common Mode Input ZCM — 1013||9 — ||pF Impedance Differential Input Impedance ZDIFF — 1013||2 — ||pF
Common Mode
Common Mode Input Voltage VCMR VSS  0.3 — VDD  1.3 V
(Note 3)
Range Common Mode Rejection Ratio CMRR 65 81 — dB VDD = 2.5V, VCM = -0.3 to 1.2V CMRR 68 84 — dB VDD = 5.5V, VCM = -0.3 to 4.2V
Open-Loop Gain
DC Open-Loop Gain AOL 88 117 — dB VDD = 2.5V, (large signal) VOUT = 0.3V to 2.2V AOL 94 126 — dB VDD = 5.5V, VOUT = 0.3V to 5.2V
Note 1:
Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS pin is toggled. Thus, 1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.
2:
Increment between adjacent VOS trim points; Figure 2-3 shows how this affects the VOS repeatability.
3:
See Figure 2-6 and Figure 2-7 for temperature effects.
4:
The ISC specifications are for design guidance only; they are not tested.  2009-2014 Microchip Technology Inc. DS20002188D-page 3 Document Outline 20 MHz, 200 µV Op Amps with mCal Features Typical Applications Design Aids Description Typical Application Circuit High Gain-Bandwidth Op Amp Portfolio Package Types 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC Electrical Specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: Digital Electrical Specifications TABLE 1-4: Temperature Specifications 1.3 Timing Diagram FIGURE 1-1: Timing Diagram. 1.4 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves 2.1 DC Signal Inputs FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage Repeatability (repeated calibration). FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-5: Input Offset Voltage vs. Output Voltage. FIGURE 2-6: Low Input Common Mode Voltage Headroom vs. Ambient Temperature. FIGURE 2-7: High Input Common Mode Voltage Headroom vs. Ambient Temperature. FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 2.5V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V. FIGURE 2-10: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-11: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-12: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V. FIGURE 2-13: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85°C. FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C. FIGURE 2-15: Input Bias Current vs. Input Voltage (below VSS). 2.2 Other DC Voltages and Currents FIGURE 2-16: Ratio of Output Voltage Headroom to Output Current. FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-18: Output Short-Circuit Current vs. Power Supply Voltage. FIGURE 2-19: Supply Current vs. Power Supply Voltage. FIGURE 2-20: Supply Current vs. Common Mode Input Voltage. FIGURE 2-21: Power-On Reset Voltages vs. Ambient Temperature. FIGURE 2-22: Normalized Internal Calibration Voltage. FIGURE 2-23: VCAL Input Resistance vs. Temperature. 2.3 Frequency Response FIGURE 2-24: CMRR and PSRR vs. Frequency. FIGURE 2-25: Open-Loop Gain vs. Frequency. FIGURE 2-26: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-27: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage. FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Output Voltage. FIGURE 2-29: Closed-Loop Output Impedance vs. Frequency. FIGURE 2-30: Gain Peaking vs. Normalized Capacitive Load. FIGURE 2-31: Channel-to-Channel Separation vs. Frequency. 2.4 Input Noise and Distortion FIGURE 2-32: Input Noise Voltage Density vs. Frequency. FIGURE 2-33: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 100 Hz. FIGURE 2-34: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 1 MHz. FIGURE 2-35: Input Noise plus Offset vs. Time with 0.1 Hz Filter. FIGURE 2-36: THD+N vs. Frequency. 2.5 Time Response FIGURE 2-37: Non-Inverting Small Signal Step Response. FIGURE 2-38: Non-Inverting Large Signal Step Response. FIGURE 2-39: Inverting Small Signal Step Response. FIGURE 2-40: Inverting Large Signal Step Response. FIGURE 2-41: The MCP621/1S/2/3/4/5/9 Family Shows No Input Phase Reversal with Overdrive. FIGURE 2-42: Slew Rate vs. Ambient Temperature. FIGURE 2-43: Maximum Output Voltage Swing vs. Frequency. 2.6 Calibration and Chip Select Response FIGURE 2-44: CAL/CS Current vs. Power Supply Voltage. FIGURE 2-45: CAL/CS Voltage, Output Voltage and Supply Current (for Side A) vs. Time with VDD = 2.5V. FIGURE 2-46: CAL/CS Voltage, Output Voltage and Supply Current (for Side A) vs. Time with VDD = 5.5V. FIGURE 2-47: CAL/CS Hysteresis vs. Ambient Temperature. FIGURE 2-48: CAL/CS Turn-On Time vs. Ambient Temperature. FIGURE 2-49: CAL/CS’s Pull-Down Resistor (RPD) vs. Ambient Temperature. FIGURE 2-50: Quiescent Current in Shutdown vs. Power Supply Voltage. FIGURE 2-51: Output Leakage Current vs. Output Voltage. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Calibration Common Mode Voltage Input 3.5 Calibrate/Chip Select Digital Input 3.6 Exposed Thermal Pad (EP) 4.0 Applications 4.1 Calibration and Chip Select FIGURE 4-1: Common-Mode Reference’s Input Circuitry. FIGURE 4-2: Setting VCM with External Resistors. 4.2 Input FIGURE 4-3: Simplified Analog Input ESD Structures. FIGURE 4-4: Protecting the Analog Inputs. FIGURE 4-5: Unity Gain Voltage Limitations for Linear Operation. 4.3 Rail-to-Rail Output FIGURE 4-6: Output Current. FIGURE 4-7: Diagram for Resistive Load Power Calculations. FIGURE 4-8: Diagram for Capacitive Load Power Calculations. 4.4 Improving Stability FIGURE 4-9: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-10: Recommended RISO Values for Capacitive Loads. FIGURE 4-11: Amplifier with Parasitic Capacitance. FIGURE 4-12: Maximum Recommended RF vs. Gain. 4.5 Power Supply 4.6 High Speed PCB Layout 4.7 Typical Applications FIGURE 4-13: Power Driver. FIGURE 4-14: Transimpedance Amplifier for an Optical Detector. FIGURE 4-15: H-Bridge Driver. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service