Datasheet LT1776 (Analog Devices) - 12

LT1776
U U W U APPLICATIONS INFORMATION
However, remember that oscillator slowdown to achieve PAC = 1/2 • VIN • IOUT • (tr + tf + 30ns) • f short-circuit protection (discussed above) is dependent tr = (VIN/1.6)ns in high dV/dt mode on FB pin behavior, and this in turn, is sensitive to FB node (VIN/0.16)ns in low dV/dt mode external impedance. Figure 2 shows the typical relation- tf = (VIN/1.6)ns (irrespective of dV/dt mode) ship between FB divider Thevenin voltage and impedance, f = switching frequency and oscillator frequency. This shows that as feedback network impedance increases beyond 10k, complete os- Total power dissipation of the die is simply the sum of cillator slowdown is not achieved, and short-circuit pro- quiescent, DC and AC losses previously calculated. tection may be compromised. And as a practical matter, PD(TOTAL) = PQ + PDC + PAC the product of FB pin bias current and larger FB network impedances will cause increasing output voltage error.
Frequency Compensation
(Nominal cancellation for 10k of FB Thevenin impedance Loop frequency compensation is performed by connect- is included internally.) ing a capacitor, or in most cases a series RC, from the output of the error amplifier (V
Thermal Considerations
C pin) to ground. Proper loop compensation may be obtained by empirical meth- Care should be taken to ensure that the worst-case input ods as described in detail in Application Note 19. Briefly, voltage and load current conditions do not cause exces- this involves applying a load transient and observing the sive die temperatures. The packages are rated at 110°C/W dynamic response over the expected range of VIN and for the 8-pin SO (S8) and 130°C/W for 8-pin PDIP (N8). ILOAD values. Quiescent power is given by: As a practical matter, a second small capacitor, directly P from the VC pin to ground is generally recommended to Q = IIN • VIN + IVCC • VOUT attenuate capacitive coupling from the VSW pin. A typical (This assumes that the VCC pin is connected to VOUT.) value for this capacitor is 100pF. (See Switch Node Con- Power loss internal to the LT1776 related to actual output siderations). current is composed of both DC and AC switching losses. These can be roughly estimated as follows:
Switch Node Considerations
DC switching losses are dominated by output switch “ON For maximum efficiency, switch rise and fall times are voltage”, i.e., made as short as practical. To prevent radiation and high frequency resonance problems, proper layout of the com- PDC = VON • IOUT • DC ponents connected to the IC is essential, especially the V power path. B field (magnetic) radiation is minimized by ON = Output switch ON voltage, typically 1V at 500mA I keeping output diode, switch pin and input bypass capaci- OUT = Output current DC = ON duty cycle tor leads as short as possible. E field radiation is kept low by minimizing the length and area of all traces connected AC switching losses are typically dominated by power lost to the switch pin (VSW). A ground plane should always be due to the finite rise time and fall time at the VSW node. used under the switcher circuitry to prevent interplane Assuming, for simplicity, a linear ramp up of both voltage coupling. and current and a current rise/fall time equal to 15ns, 12