Datasheet ADSP-BF592 (Analog Devices) - 35

link to page 35 link to page 35 link to page 35
ADSP-BF592 JTAG Test And Emulation Port Timing
Table 31 and Figure 24 describe JTAG port operations.
Table 31. JTAG Port Timing VDDEXT VDDEXT 1.8V Nominal 2.5 V/3.3V Nominal Parameter Min Max Min Max Unit
Timing Requirements tTCK TCK Period 20 20 ns tSTAP TDI, TMS Setup Before TCK High 4 4 ns tHTAP TDI, TMS Hold After TCK High 4 4 ns tSSYS System Inputs Setup Before TCK High1 4 5 ns tHSYS System Inputs Hold After TCK High1 5 5 ns tTRSTW TRST Pulse Width2 (measured in TCK cycles) 4 4 TCK Switching Characteristics tDTDO TDO Delay from TCK Low 10 10 ns tDSYS System Outputs Delay After TCK Low3 13 13 ns 1 System inputs = SCL, SDA, PF15–0, PG15–0, PH2–0, TCK, NMI, BMODE3–0, PG. 2 50 MHz maximum. 3 System outputs = CLKOUT, SCL, SDA, PF15–0, PG15–0, PH2–0, TDO, EMU, EXT_WAKE.
tTCK TCK tSTAP tHTAP TMS TDI tDTDO TDO tSSYS tHSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS
Figure 24. JTAG Port Timing Rev. B | Page 35 of 44 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory L1 Utility ROM Custom ROM (Optional) I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Watchdog Timer Timers Serial Ports Serial Peripheral Interface (SPI) Ports UART Port Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF592 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 64-Lead LFCSP Lead Assignment Outline Dimensions Automotive Products Ordering Guide