Datasheet ADSP-BF522, ADSP-BF523, ADSP-BF524, ADSP-BF525, ADSP-BF526, ADSP-BF527 (Analog Devices) - 4

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ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
regulator provides a range of core voltage levels when supplied The compute register file contains eight 32-bit registers. When from VDDEXT. The voltage regulator can be bypassed at the user's performing compute operations on 16-bit operand data, the discretion. register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported
BLACKFIN PROCESSOR CORE
register file and instruction constant fields. As shown in Figure 2, the Blackfin processor core contains two Each MAC can perform a 16-bit by 16-bit multiply in each 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, cycle, accumulating the results into the 40-bit accumulators. four video ALUs, and a 40-bit shifter. The computation units Signed and unsigned formats, rounding, and saturation process 8-, 16-, or 32-bit data from the register file. are supported.
ADDRESS ARITHMETIC UNIT SP I3 L3 B3 M3 FP I2 L2 B2 M2 P5 I1 L1 B1 M1 DAG1 P4 I0 L0 B0 M0 DAG0 P3 P2 DA1 32 P1 DA0 32 P0 Y 32 32 RAB PREG MEMOR TO SD 32 LD1 32 ASTAT 32 LD0 32 32 SEQUENCER R7.H R7.L R6.H R6.L R5.H R5.L ALIGN 16 16 R4.H R4.L 8 8 8 8 R3.H R3.L DECODE R2.H R2.L R1.H R1.L BARREL R0.H R0.L SHIFTER 40 40 LOOP BUFFER A0 40 40 A1 CONTROL UNIT 32 32 DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core The ALUs perform a traditional set of arithmetic and logical The 40-bit shifter can perform shifts and rotates and is used to operations on 16-bit or 32-bit data. In addition, many special support normalization, field extract, and field deposit instructions are included to accelerate various signal processing instructions. tasks. These include bit operations such as field extract and pop- The program sequencer controls the flow of instruction execu- ulation count, modulo 232 multiply, divide primitives, saturation tion, including instruction alignment and decoding. For and rounding, and sign/exponent detection. The set of video program flow control, the sequencer supports PC relative and instructions include byte alignment and packing operations, indirect conditional jumps (with static branch prediction), and 16-bit and 8-bit adds with clipping, 8-bit average operations, subroutine calls. Hardware is provided to support zero-over- and 8-bit subtract/absolute value/accumulate (SAA) operations. head looping. The architecture is fully interlocked, meaning that Also provided are the compare/select and vector search the programmer need not manage the pipeline when executing instructions. instructions with data dependencies. For certain instructions, two 16-bit ALU operations can be per- The address arithmetic unit provides two addresses for simulta- formed simultaneously on register pairs (a 16-bit high half and neous dual fetches from memory. It contains a multiported 16-bit low half of a compute register). If the second ALU is used, register file consisting of four sets of 32-bit index, modify, quad 16-bit operations are possible. Rev. D | Page 4 of 88 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory NAND Flash Controller (NFC) One-Time Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports Serial Peripheral Interface (SPI) Port UART Ports TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode USB On-The-Go Dual-Role Device Controller Code Security with Lockbox Secure Technology Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Lockbox Secure Technology Disclaimer Signal Descriptions Specifications Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Clock Related Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Clock Related Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing NAND Flash Controller Interface Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing HOSTDP A/C Timing- Host Read Cycle HOSTDP A/C Timing- Host Write Cycle 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 289-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide