Datasheet ADE7816 (Analog Devices) - 45

Data Sheet ADE7816 Table 26. ACCMODE Register (Address 0xE701) Default Bits Bit Name Value Description
7 REVRPSEL 0x0 0: the sign of the reactive power is monitored on the A, B, and C channels. 1: the sign of the reactive power is monitored on the D, E, and F channels. Bit 14 (CHANNEL_SEL) of COMPMODE must be set to the same current channels. 6 REVAPSEL 0x0 0: the sign of the active power is monitored on the A, B, and C channels. 1: the sign of the active power is monitored on the D, E, and F channels. Bit 14 (CHANNEL_SEL) of COMPMODE must be set to the same current channels. [5:4] Reserved 0x00 These bits should be ignored and not modified. [3:2] VARACC[1:0] 0x00 00: signed accumulation for all reactive power measurements. 01: reserved. 10: reserved. 11: reserved. [1:0] WATTACC[1:0] 0x00 00: signed accumulation for all active power measurements. 01: reserved. 10: reserved. 11: reserved.
Table 27. LCYCMODE Register (Address 0xE702) Default Bits Bit Name Value Description
7 Reserved 0x0 Reserved. This bit does not control any functionality. 6 RSTREAD 0x1 Enables read-with-reset for all energy registers. Note that this bit has no function in line cycle accumulation mode and should be set to 0 when this mode is in use. [5:4] Reserved 0x0 These bits should be ignored. 3 ZX_SEL 0x0 Enables the voltage channel zero-crossing counter for line cycle accumulation mode. 2 Reserved 0x0 These bits should be ignored. 1 LVAR 0x0 Enables the reactive energy line cycle accumulation mode. 0 LWATT 0x0 Enables the active energy line cycle accumulation mode.
Table 28. HSDC_CFG Register (Address 0xE706) Default Bits Bit Name Value Description
[7:6] Reserved 0x00 These bits should be ignored. 5 HSAPOL 0x0 0: SS/HSA output pin is active low (default). 1: SS/HSA output pin is active high. [4:3] HXFER[1:0] 0x00 00 = reserved. 01 = HSDC transmits current and voltage waveform data. 10 = reserved. 11 = reserved. 2 HGAP 0x0 0: no gap is introduced between packages (default). 1: a gap of seven HCLK cycles is introduced between packages. 1 HSIZE 0x0 0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first (default). 1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first. 0 HCLK 0x0 0: HSCLK = 8 MHz (default). 1: HSCLK = 4 MHz.
Table 29. CONFIG2 Register (Address 0xEC01) Default Bits Bit Name Value Description
[7:2] Reserved 0x0 These bits should be ignored. 1 I2C_LOCK 0x0 Serial port lock. 0 EXTREFEN 0x0 Set to 1 to use with an external reference. Rev. B | Page 45 of 48 Document Outline Features General Description Functional Block Diagram Revision History Specifications Timing Characteristics I2C-Compatible Interface Timing SPI Interface Timing HSDC Interface Timing Load Circuit for All Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuit Terminology Quick Start Inputs Power and Ground VDD and AGND, DGND Reference Circuit REFIN/OUT Reset Hardware Reset Software Reset Functionality CLKIN and CLKOUT Analog Inputs Input Pins PGA Gain Digital Integrator Antialiasing Filters Energy Measurements Starting and Stopping the DSP Active Energy Measurement Definition of Active Power and Active Energy Active Energy Registers Active Energy Threshold Energy Accumulation and Register Roll-Over Reactive Energy Measurement Definition of Reactive Power and Reactive Energy Reactive Energy Registers Reactive Energy Threshold Reactive Energy Accumulation and Register Roll-Over Line Cycle Accumulation Mode Root Mean Square Measurement No Load Detection Setting the No Load Thresholds No Load Interrupt Energy Calibration Channel Matching Energy Gain Calibration Energy Offset Calibration Energy Phase Calibration RMS Offset Calibration Power Quality Features Selecting a Current Channel Group Instantaneous Waveforms Zero-Crossing Detection Zero-Crossing Detection Zero-Crossing Timeout Peak Detection Setting the PEAKCYC Register Overcurrent and Overvoltage Detection Setting the OVLVL and OILVL Registers Overvoltage and Overcurrent Interrupts Indication of Power Direction Angle Measurements Period Measurement Voltage Sag Detection Setting the SAGCYC Register Setting the SAGLVL Register Voltage Sag Interrupt Checksum Layout Guidelines Crystal Circuit Outputs Interrupts Communication Serial Interface Selection I2C-Compatible Interface I2C Write Operation I2C Read Operation SPI-Compatible Interface SPI Read Operation SPI Write Operation HSDC Interface Registers Register Protection Register Format Register Maps Register Descriptions Interrupt Enable and Interrupt Status Registers Outline Dimensions Ordering Guide