Datasheet ADN8835 (Analog Devices) - 9

Data Sheet ADN8835 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
100 100 90 90 80 80 70 70 %) %) ( 60 ( 60 NCY 50 NCY E 50 E ICI ICI F 40 F 40 F F E E 30 30 20 20 LOAD = 2Ω 10 LOAD = 1Ω 10 VIN = 5V LOAD = 0.5Ω VIN = 3.3V 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0
007
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
006
TEC CURRENT (A)
14174-
TEC CURRENT (A)
14174- Figure 5. Efficiency vs. TEC Current at VIN = 3.3 V at Various Loads in Cooling Figure 8. Efficiency vs. TEC Current at VIN = 3.3 V and 5 V in Heating Mode Mode with 1 Ω Load
100 3.0 90 2.5 80 A) ( 70 NT 2.0 %) ( 60 NCY 50 E 1.5 C CURRE E ICI T F 40 F E UM 1.0 30 IM AX M 20 LOAD = 2Ω 0.5 LOAD = 2Ω 10 LOAD = 1Ω LOAD = 1Ω LOAD = 0.5Ω LOAD = 0.5Ω 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0
008
2.7 3.7 4.7
009
TEC CURRENT (A)
14174-
INPUT VOLTAGE AT PVIN (V)
14174- Figure 6. Efficiency vs. TEC Current at VIN = 3.3 V at Various Loads in Heating Figure 9. Maximum TEC Current vs. Input Voltage at PVIN at Various Loads, Mode Without Voltage and Current Limit
100 0.20 90 0.15 80 0.10 70 %) %) 0.05 ( 60 R ( NCY 50 E 0 RRO ICI E F 40 F F RE –0.05 E V 30 –0.10 20 –0.15 10 VIN = 5V NO LOAD VIN = 3.3V 5mA LOAD 0 –0.20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
005
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
010
TEC CURRENT (A)
14174-
SUPPLY VOLTAGE (V)
14174- Figure 7. Efficiency vs. TEC Current at VIN = 3.3 V and 5 V in Cooling Mode Figure 10. VREF Line Regulation

with 1 Ω Load Rev. B | Page 9 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG PID CONTROL DIGITAL PID CONTROL POWERING THE CONTROLLER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8835 Devices TEMPERATURE LOCK INDICATOR SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION SIGNAL FLOW THERMISTOR SETUP THERMISTOR AMPLIFIER (CHOPPER 1) PID COMPENSATION AMPLIFIER (CHOPPER 2) MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Losses (PSW) Transition Losses (PTRAN) Linear Regulator Power Dissipation THERMAL CONSIDERATION PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE