Datasheet ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 (Analog Devices) - 3
| Fabricante | Analog Devices |
| Descripción | SHARC Processor |
| Páginas / Página | 71 / 3 — ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489. GENERAL … |
| Revisión | H |
| Formato / tamaño de archivo | PDF / 1.9 Mb |
| Idioma del documento | Inglés |
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489. GENERAL DESCRIPTION. Table 1. Processor Benchmarks. Speed
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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 GENERAL DESCRIPTION
The ADSP-2148x SHARC® processors are members of the
Table 1. Processor Benchmarks
SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source code
Speed Speed
compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x,
Benchmark Algorithm (at 400 MHz) (at 450 MHz)
ADSP-2146x, ADSP-2147x and ADSP-2116x DSPs, as well as 1024 Point Complex FFT 23 μs 20.44 μs with first generation ADSP-2106x SHARC processors in SISD (Radix 4, with Reversal) (single-instruction, single-data) mode. The ADSP-2148x pro- FIR Filter (per Tap)1 1.25 ns 1.1 ns cessors are 32-bit/40-bit floating point processors optimized for IIR Filter (per Biquad)1 5 ns 4.43 ns high performance audio applications with large on-chip SRAM, Matrix Multiply (Pipelined) multiple internal buses to eliminate I/O bottlenecks, and an [3 × 3] × [3 × 1] 11.25 ns 10.0 ns innovative digital applications interface (DAI). [4 × 4] × [4 × 1] 20 ns 17.78 ns Table 1 shows performance benchmarks for the ADSP-2148x Divide (y/×) 7.5 ns 6.67 ns processors. Table 2 shows the features of the individual product offerings. Inverse Square Root 11.25 ns 10.0 ns 1 Assumes two files in multichannel SIMD mode
Table 2. ADSP-2148x Family Features Feature ADSP-21483 ADSP-21486 ADSP-21487 ADSP-21488 ADSP-21489
Maximum Instruction Rate 400 MHz 400 MHz 450 MHz 400 MHz 450 MHz RAM 3 Mbits 5 Mbits 2/3 Mbits1 5 Mbits ROM 4 Mbits No Audio Decoders in ROM2 Yes No Pulse-Width Modulation 4 Units (3 Units on 100-Lead Packages) DTCP Hardware Accelerator Contact Analog Devices External Port Interface (SDRAM, AMI)3 Yes (16-bit) AMI Only Yes (16-bit) Serial Ports 8 Direct DMA from SPORTs to Yes External Port (External Memory) FIR, IIR, FFT Accelerator Yes Watchdog Timer Yes (176-Lead Package Only) MediaLB Interface Automotive Models Only IDP/PDAP Yes UART 1 DAI (SRU)/DPI (SRU2) Yes S/PDIF Transceiver Yes SPI Yes TWI 1 SRC Performance4 –128 dB Thermal Diode Yes VISA Support Yes Package3 176-Lead LQFP EPAD 176-Lead LQFP EPAD 176-Lead LQFP EPAD 176-Lead LQFP EPAD 100-Lead LQFP EPAD 88-Lead LFCSP5 100-Lead LQFP EPAD 100-Lead LQFP EPAD5 88-Lead LFCSP5 88-Lead LFCSP5 1 See Ordering Guide on Page 70. 2 ROM is factory programmed with latest multichannel audio decoding and post-processing algorithms from Dolby® Labs and DTS®. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Visit www.analog.com for complete information. 3 The 100-lead and 88-lead packages do not contain an external port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin Function Descriptions on Page 14. The ADSP-21486 processor in the 176-lead package also does not contain a SDRAM controller. For more information, see 176-Lead LQFP_EP Lead Assignment on page 62. 4 Some models have –140 dB performance. For more information, see Ordering Guide on page 70. 5 Only available up to 400 MHz. See Ordering Guide on Page 70 for details. Rev. H | Page 3 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 GENERAL DESCRIPTION
The ADSP-2148x SHARC® processors are members of the
Table 1. Processor Benchmarks
SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source code
Speed Speed
compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x,
Benchmark Algorithm (at 400 MHz) (at 450 MHz)
ADSP-2146x, ADSP-2147x and ADSP-2116x DSPs, as well as 1024 Point Complex FFT 23 μs 20.44 μs with first generation ADSP-2106x SHARC processors in SISD (Radix 4, with Reversal) (single-instruction, single-data) mode. The ADSP-2148x pro- FIR Filter (per Tap)1 1.25 ns 1.1 ns cessors are 32-bit/40-bit floating point processors optimized for IIR Filter (per Biquad)1 5 ns 4.43 ns high performance audio applications with large on-chip SRAM, Matrix Multiply (Pipelined) multiple internal buses to eliminate I/O bottlenecks, and an [3 × 3] × [3 × 1] 11.25 ns 10.0 ns innovative digital applications interface (DAI). [4 × 4] × [4 × 1] 20 ns 17.78 ns Table 1 shows performance benchmarks for the ADSP-2148x Divide (y/×) 7.5 ns 6.67 ns processors. Table 2 shows the features of the individual product offerings. Inverse Square Root 11.25 ns 10.0 ns 1 Assumes two files in multichannel SIMD mode
Table 2. ADSP-2148x Family Features Feature ADSP-21483 ADSP-21486 ADSP-21487 ADSP-21488 ADSP-21489
Maximum Instruction Rate 400 MHz 400 MHz 450 MHz 400 MHz 450 MHz RAM 3 Mbits 5 Mbits 2/3 Mbits1 5 Mbits ROM 4 Mbits No Audio Decoders in ROM2 Yes No Pulse-Width Modulation 4 Units (3 Units on 100-Lead Packages) DTCP Hardware Accelerator Contact Analog Devices External Port Interface (SDRAM, AMI)3 Yes (16-bit) AMI Only Yes (16-bit) Serial Ports 8 Direct DMA from SPORTs to Yes External Port (External Memory) FIR, IIR, FFT Accelerator Yes Watchdog Timer Yes (176-Lead Package Only) MediaLB Interface Automotive Models Only IDP/PDAP Yes UART 1 DAI (SRU)/DPI (SRU2) Yes S/PDIF Transceiver Yes SPI Yes TWI 1 SRC Performance4 –128 dB Thermal Diode Yes VISA Support Yes Package3 176-Lead LQFP EPAD 176-Lead LQFP EPAD 176-Lead LQFP EPAD 176-Lead LQFP EPAD 100-Lead LQFP EPAD 88-Lead LFCSP5 100-Lead LQFP EPAD 100-Lead LQFP EPAD5 88-Lead LFCSP5 88-Lead LFCSP5 1 See Ordering Guide on Page 70. 2 ROM is factory programmed with latest multichannel audio decoding and post-processing algorithms from Dolby® Labs and DTS®. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Visit www.analog.com for complete information. 3 The 100-lead and 88-lead packages do not contain an external port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin Function Descriptions on Page 14. The ADSP-21486 processor in the 176-lead package also does not contain a SDRAM controller. For more information, see 176-Lead LQFP_EP Lead Assignment on page 62. 4 Some models have –140 dB performance. For more information, see Ordering Guide on page 70. 5 Only available up to 400 MHz. See Ordering Guide on Page 70 for details. Rev. H | Page 3 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide