Datasheet SR6P3EC4 (STMicroelectronics) - 7
| Fabricante | STMicroelectronics |
| Descripción | 32-bit Arm Cortex R52+ automotive integration MCU 4 Cortex R52+ cores, 19.5 MB xMemory, 1.8 MB RAM, with embedded virtualization, safety, and security in FPBGA292 package |
| Páginas / Página | 10 / 7 — SR6P3EC4 SR6P3EC6. Revision history. Table 3. Document revision history. … |
| Formato / tamaño de archivo | PDF / 572 Kb |
| Idioma del documento | Inglés |
SR6P3EC4 SR6P3EC6. Revision history. Table 3. Document revision history. Date. Version. Changes. DB5468. Rev 4. page 7/10
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SR6P3EC4 SR6P3EC6 Revision history Table 3. Document revision history Date Version Changes
20-Jan-2025 1 Initial release. • Peripheral, I/O, and communication interfaces: added "1 dual-channel 21-Jan-2025 2 FlexRay controller" and "Enhanced interconnection with GTM time..." • In the whole document, – removed the SR6P3EC5 part number and the associated package FPBGA348: document titles, package silhouette, product summary, Table 1. SR6P3EC4 and SR6P3EC6 overview – minor editorial changes • changed classification level to "public" • Highlights: updated 15-Jan-2026 3 • Cores and accelerators: updated section title • Memories: updated • Peripheral, I/O, and communication interfaces: updated • Table 1. SR6P3EC4 and SR6P3EC6 overview: updated • Figure 1. Block diagram: updated • Table 2. Ordering information scheme: added • Glossary updated The 10BASE-T1S feature is optional. Its availability depends on the ordered part number: • Peripheral, I/O, and communication interfaces: updated 18-Feb-2026 4 • Table 1. SR6P3EC4 and SR6P3EC6 overview: added footnote • Figure 1. Block diagram: added footnote • Table 2. Ordering information scheme: added new "Device option" code
DB5468
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Rev 4 page 7/10
Document Outline SR6P3EC4 SR6P3EC6 Features 1 Introduction 1.1 Document overview 1.2 Description 1.3 Block diagram 2 Ordering information Revision history Glossary ADC AEC AES ASIL ATOM CAN CAN FD® CAN XL® CPU CRC DCF DMA DSP eDMA EMC EVITA FCCU FPBGA FPU GB GPIO GTM HSM I/O I2C IEC IEEE IPv4 IPv6 ISO JTAG KB LIN LVDS M_TTCAN MB MCAN MCS MCU MII NoC NPU NVM OA3p OS OSR OTA PHY PLL PSI5 RAM RGMII RMII SAR SDADC SENT SIMD SIPI SPI SPIQ SRAM SRC ST SWD TIM TIO TOM UART VLAN xMemory XS_CAN
SR6P3EC4 SR6P3EC6 Revision history Table 3. Document revision history Date Version Changes
20-Jan-2025 1 Initial release. • Peripheral, I/O, and communication interfaces: added "1 dual-channel 21-Jan-2025 2 FlexRay controller" and "Enhanced interconnection with GTM time..." • In the whole document, – removed the SR6P3EC5 part number and the associated package FPBGA348: document titles, package silhouette, product summary, Table 1. SR6P3EC4 and SR6P3EC6 overview – minor editorial changes • changed classification level to "public" • Highlights: updated 15-Jan-2026 3 • Cores and accelerators: updated section title • Memories: updated • Peripheral, I/O, and communication interfaces: updated • Table 1. SR6P3EC4 and SR6P3EC6 overview: updated • Figure 1. Block diagram: updated • Table 2. Ordering information scheme: added • Glossary updated The 10BASE-T1S feature is optional. Its availability depends on the ordered part number: • Peripheral, I/O, and communication interfaces: updated 18-Feb-2026 4 • Table 1. SR6P3EC4 and SR6P3EC6 overview: added footnote • Figure 1. Block diagram: added footnote • Table 2. Ordering information scheme: added new "Device option" code
DB5468
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Rev 4 page 7/10
Document Outline SR6P3EC4 SR6P3EC6 Features 1 Introduction 1.1 Document overview 1.2 Description 1.3 Block diagram 2 Ordering information Revision history Glossary ADC AEC AES ASIL ATOM CAN CAN FD® CAN XL® CPU CRC DCF DMA DSP eDMA EMC EVITA FCCU FPBGA FPU GB GPIO GTM HSM I/O I2C IEC IEEE IPv4 IPv6 ISO JTAG KB LIN LVDS M_TTCAN MB MCAN MCS MCU MII NoC NPU NVM OA3p OS OSR OTA PHY PLL PSI5 RAM RGMII RMII SAR SDADC SENT SIMD SIPI SPI SPIQ SRAM SRC ST SWD TIM TIO TOM UART VLAN xMemory XS_CAN