Datasheet IP101G (IC Plus)

IP101G Data Sheet
Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver (85nm/Extreme Low PW, PWMT® and EMIMT®) Features General Description
z 10/100Mbps IEEE 802.3/802.3u compliant z Package and operation temperature Fast Ethernet transceiver IP101G: dice, 0~70℃ z Supports 100Base-TX/FX Media Interface IP101GA: 48LQFP, 0~70℃ z Supports MII/ RMII Interface IP101GR: 32QFN, 0~70℃ z Supports Auto MDI/MDIX function IP101GRI: 32QFN, -40~85℃ z Power Management Tool - APS, auto power saving while Link-off IP101G is an IEEE 802.3/802.3u compliant - 802.3az, protocol based power saving single-port Fast Ethernet Transceiver for both - WOL+, light traffic power saving 100Mbps and 10Mbps operations. It supports - PWD, force-off power saving Auto MDI/MDIX function to simplify the network - Supports MII with LPI for RX and TX installation and reduce the system maintenance - Supports RMII with LPI for RX cost. To improve the system performance, z Supports Base Line Wander compensation IP101G provides a hardware interrupt pin to z Supports Interrupt function indicate the link, speed and duplex status z Built in synchronization FIFO to support change. IP101G provides Media Independent jumbo frame size up to 12KB in MII mode (10KB Interface (MII) or Reduced Media Independent in RMII 100Mbps mode) Interface (RMII) to connect with different types z Supports MDC and MDIO to communicate of 10/100Mbps Media Access Controller (MAC). with the MAC IP101G is designed to use category 5 z EMI Management Tool unshielded twisted-pair cable or Fiber-Optic - F/W based control cables connecting to other LAN devices. A - 4 levels for mapping the difference layout PECL interface is supported to connect with an length on the PCB external 100Base-FX fiber optical transceiver. z Single 3.3V power supply Except good performance, reliability, rich power z Built-in Vcore regulator saving method and extreme low operating z DSP-based PHY Transceiver technology current, IP101G provides a serial tool for z System Debug Assistant Tool system designers to complete their projects - 16 bit RX counter easily. They are System Debug Assistant Tool - 9 bit RXError/CRC counter and EMI Management Tool. - Isolate MII/RMII IP101G is fabricated with advanced CMOS - RX to TX Loopback (85nm) technology and design is based on - Loopback MII/RMII IC Plus’s 5th Ethernet-PHY architecture, this z Using either 25MHz crystal/oscillator or feature makes IP101G consumes very low 50MHz oscillator REF_CLK as clock source power. Such as in the full load operation z Built-in 49.9ohm resistors for simplifying (100Mbps_FDX), it only takes below 0.15W. BOM IP101GA / IP101GR&IP101GRI are available in z Flexible LED display 48LQFP/32QFN, lead-free package. z Process: 85nm * EMIMT: Patent under apply.
Application
■ NAS ■ Game console ■ Network Printers and Servers ■ IP and Video Phone ■ IP Set-Top Box ■ PoE ■ IP/Smart TV ■ Telecom Fiber device 1/66 May 20, 2014 Copyright © 2011, IC Plus Corp. IP101G-DS-R01 Document Outline Features comparison between IP101G and IP101A/IP101AH 1 Pin diagram 2 Dice pad information 3 Pin description 3.1 IP101GA pin description 3.2 IP101GR/GRI pin description 4 Register Descriptions 4.1 Register Page mode Control Register 4.2 MII Registers 4.3 MMD Control Register 4.4 MMD Data Register 4.5 RX Counter Register 4.6 LED Pin Control Register 4.7 WOL+ Control Register 4.8 UTP PHY Specific Control Register 4.9 Digital IO Pin Control Register 5 Function Description 5.1 Major Functional Block Description 5.1.1 Transmission Description 5.1.2 MII and Management Control Interface 5.1.3 RMII Interface 5.1.4 Flexible Clock Source 5.1.5 Auto-Negotiation and Related Information 5.1.6 Auto-MDIX function 5.2 PHY Address Configuration 5.3 Power Management Tool 5.3.1 Auto Power Saving Mode 5.3.2 IEEE802.3az EEE (Energy Efficient Ethernet) 5.3.3 Force power down 5.3.4 WOL+ operation mode 5.4 LED Mode Configuration 5.5 LED Blink Timing 5.6 Repeater Mode 5.7 Interrupt 5.8 Miscellaneous 5.9 Serial Management Interface 5.10 Fiber Mode Setting 5.11 Jumbo Frame 6 Layout Guideline 6.1 General Layout Guideline 6.2 Twisted Pair recommendation 7 Electrical Characteristics 7.1 Absolute Maximum Rating 7.2 DC Characteristics 7.3 Crystal Specifications 7.4 AC Timing 7.4.1 Reset, Pin Latched-in, Clock and Power Source 7.4.2 MII Timing 7.4.3 RMII Timing 7.4.4 SMI Timing 7.4.5 MDI to MII latency delay time 7.5 Thermal Data 8 Order Information 9 Physical Dimensions 9.1 48-PIN LQFP 9.2 32-PIN QFN