Datasheet IP101G (IC Plus) - 5
| Fabricante | IC Plus |
| Descripción | Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver |
| Páginas / Página | 66 / 5 — List of Tables |
| Formato / tamaño de archivo | PDF / 1.7 Mb |
| Idioma del documento | Inglés |
List of Tables
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List of Tables
Table 1 Features comparison between IP101G and IP101A/IP101AH...7 Table 2 Register Map...19 Table 3 Flexible Clock Source Setting...45 Table 4 PHY Address Configuration ..47 Table 5 PHY Address Configuration by register ..47 Table 6 WOL+ operation mode..50 Table 7 LED Mode 1 Function ...53 Table 8 LED Mode 2 Function ...53 Table 9 LED Blink Timing ..53 Table 10 SMI Format ...54 Table 11 DC Characteristics ..57 Table 12 I/O Electrical Characteristics...57 Table 13 Pin Latched-in Configuration Resistor ..58 Table 14 Crystal Specifications..58 Table 15 Reset, Pin Latched-in, Clock and Power Source Timing Requirements ..59 Table 16 MII Transmit Timing Requirements ...60 Table 17 MII Receive Timing Specifications ..60 Table 18 RMII Transmit Timing Requirements ..61 Table 19 RMII Receive Timing Specifications ...61 Table 20 SMI Timing Requirements ..62 Table 21 MDI to MII latency delay time ...62 Table 22 Thermal Data ..63 Table 23 Part Number and Package ...63 5/66 May 20, 2014 Copyright © 2011, IC Plus Corp. IP101G-DS-R01 Document Outline Features comparison between IP101G and IP101A/IP101AH 1 Pin diagram 2 Dice pad information 3 Pin description 3.1 IP101GA pin description 3.2 IP101GR/GRI pin description 4 Register Descriptions 4.1 Register Page mode Control Register 4.2 MII Registers 4.3 MMD Control Register 4.4 MMD Data Register 4.5 RX Counter Register 4.6 LED Pin Control Register 4.7 WOL+ Control Register 4.8 UTP PHY Specific Control Register 4.9 Digital IO Pin Control Register 5 Function Description 5.1 Major Functional Block Description 5.1.1 Transmission Description 5.1.2 MII and Management Control Interface 5.1.3 RMII Interface 5.1.4 Flexible Clock Source 5.1.5 Auto-Negotiation and Related Information 5.1.6 Auto-MDIX function 5.2 PHY Address Configuration 5.3 Power Management Tool 5.3.1 Auto Power Saving Mode 5.3.2 IEEE802.3az EEE (Energy Efficient Ethernet) 5.3.3 Force power down 5.3.4 WOL+ operation mode 5.4 LED Mode Configuration 5.5 LED Blink Timing 5.6 Repeater Mode 5.7 Interrupt 5.8 Miscellaneous 5.9 Serial Management Interface 5.10 Fiber Mode Setting 5.11 Jumbo Frame 6 Layout Guideline 6.1 General Layout Guideline 6.2 Twisted Pair recommendation 7 Electrical Characteristics 7.1 Absolute Maximum Rating 7.2 DC Characteristics 7.3 Crystal Specifications 7.4 AC Timing 7.4.1 Reset, Pin Latched-in, Clock and Power Source 7.4.2 MII Timing 7.4.3 RMII Timing 7.4.4 SMI Timing 7.4.5 MDI to MII latency delay time 7.5 Thermal Data 8 Order Information 9 Physical Dimensions 9.1 48-PIN LQFP 9.2 32-PIN QFN
List of Tables
Table 1 Features comparison between IP101G and IP101A/IP101AH...7 Table 2 Register Map...19 Table 3 Flexible Clock Source Setting...45 Table 4 PHY Address Configuration ..47 Table 5 PHY Address Configuration by register ..47 Table 6 WOL+ operation mode..50 Table 7 LED Mode 1 Function ...53 Table 8 LED Mode 2 Function ...53 Table 9 LED Blink Timing ..53 Table 10 SMI Format ...54 Table 11 DC Characteristics ..57 Table 12 I/O Electrical Characteristics...57 Table 13 Pin Latched-in Configuration Resistor ..58 Table 14 Crystal Specifications..58 Table 15 Reset, Pin Latched-in, Clock and Power Source Timing Requirements ..59 Table 16 MII Transmit Timing Requirements ...60 Table 17 MII Receive Timing Specifications ..60 Table 18 RMII Transmit Timing Requirements ..61 Table 19 RMII Receive Timing Specifications ...61 Table 20 SMI Timing Requirements ..62 Table 21 MDI to MII latency delay time ...62 Table 22 Thermal Data ..63 Table 23 Part Number and Package ...63 5/66 May 20, 2014 Copyright © 2011, IC Plus Corp. IP101G-DS-R01 Document Outline Features comparison between IP101G and IP101A/IP101AH 1 Pin diagram 2 Dice pad information 3 Pin description 3.1 IP101GA pin description 3.2 IP101GR/GRI pin description 4 Register Descriptions 4.1 Register Page mode Control Register 4.2 MII Registers 4.3 MMD Control Register 4.4 MMD Data Register 4.5 RX Counter Register 4.6 LED Pin Control Register 4.7 WOL+ Control Register 4.8 UTP PHY Specific Control Register 4.9 Digital IO Pin Control Register 5 Function Description 5.1 Major Functional Block Description 5.1.1 Transmission Description 5.1.2 MII and Management Control Interface 5.1.3 RMII Interface 5.1.4 Flexible Clock Source 5.1.5 Auto-Negotiation and Related Information 5.1.6 Auto-MDIX function 5.2 PHY Address Configuration 5.3 Power Management Tool 5.3.1 Auto Power Saving Mode 5.3.2 IEEE802.3az EEE (Energy Efficient Ethernet) 5.3.3 Force power down 5.3.4 WOL+ operation mode 5.4 LED Mode Configuration 5.5 LED Blink Timing 5.6 Repeater Mode 5.7 Interrupt 5.8 Miscellaneous 5.9 Serial Management Interface 5.10 Fiber Mode Setting 5.11 Jumbo Frame 6 Layout Guideline 6.1 General Layout Guideline 6.2 Twisted Pair recommendation 7 Electrical Characteristics 7.1 Absolute Maximum Rating 7.2 DC Characteristics 7.3 Crystal Specifications 7.4 AC Timing 7.4.1 Reset, Pin Latched-in, Clock and Power Source 7.4.2 MII Timing 7.4.3 RMII Timing 7.4.4 SMI Timing 7.4.5 MDI to MII latency delay time 7.5 Thermal Data 8 Order Information 9 Physical Dimensions 9.1 48-PIN LQFP 9.2 32-PIN QFN