Datasheet Texas Instruments ADS5271IPFP — Ficha de datos

FabricanteTexas Instruments
SerieADS5271
Numero de parteADS5271IPFP
Datasheet Texas Instruments ADS5271IPFP

Convertidor analógico a digital (ADC) de ocho canales, 12 bits y 50 MSPS 80-HTQFP -40 a 85

Hojas de datos

8-Channel, 12-Bit, 50MSPS Analog-to-Digital Converter with Serial LVDS Interface datasheet
PDF, 1.3 Mb, Revisión: C, Archivo publicado: enero 6, 2009
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin80
Package TypePFP
Industry STD TermHTQFP
JEDEC CodeS-PQFP-G
Package QTY96
CarrierJEDEC TRAY (10+1)
Device MarkingADS5271IPFP
Width (mm)12
Length (mm)12
Thickness (mm)1
Pitch (mm).5
Max Height (mm)1.2
Mechanical DataDescargar

Paramétricos

# Input Channels8
Analog Input BW300 MHz
ArchitecturePipeline
DNL(Max)0.5 +/-LSB
DNL(Typ)0.5 +/-LSB
ENOB11.3 Bits
INL(Max)0.6 +/-LSB
INL(Typ)0.6 +/-LSB
Input BufferNo
Input Range2 Vp-p
InterfaceParallel LVDS
Operating Temperature Range-40 to 85 C
Package GroupHTQFP
Package Size: mm2:W x L80HTQFP: 196 mm2: 14 x 14(HTQFP) PKG
Power Consumption(Typ)957 mW
RatingCatalog
Reference ModeExt,Int
Resolution12 Bits
SFDR85 dB
SINAD70 dB
SNR70.5 dB
Sample Rate(Max)50 MSPS

Plan ecológico

RoHSObediente

Kits de diseño y Módulos de evaluación

  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200 Low-Cost Portable Power Supply Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)

Notas de aplicación

  • Using the ADSDeSer-50EVM to Deserialize ADS527x 10-Bit Outputs
    PDF, 104 Kb, Archivo publicado: jul 8, 2004
    The ADSDeSer-50EVM provides an direct means of examining the serialized 10-bit data output from the ADS527x families of serialized low voltage differential signal(LVDS) data converters by deserializing the data and converting to a parallel data port. This application report discusses the process of reading deserialized 10-bit data outputs from the ADS527x family using the ADSDeSer50-EVM.
  • LVDS Outputs on the ADS527x
    PDF, 236 Kb, Archivo publicado: jun 10, 2004
  • Interfacing High-Speed LVDS Outputs of the ADS527x/ADS524x
    PDF, 67 Kb, Archivo publicado: feb 23, 2005
    The ADS527x and ADS524x families of devices are high-performance octal/quad channel analog-to-digital converters, ideal for the highest system density. Serial low voltage differential signaling (LVDS) outputs reduce the number of I/O interfaces required, power and overall package size. These device families are rated to work from sampling rates of 20MSPS to 70MSPS, corresponding to data rates of 2
  • Interfacing the VCA8613 with High-Speed ADCs
    PDF, 78 Kb, Archivo publicado: abr 5, 2005
    The VCA8613 is an 8-channel variable gain amplifier ideally suited for portable and mid-range ultrasound applications. Each channel consists of a Low Noise Amplifier (LNA) and a Variable Gain Amplifier (VGA). The VGA contains two parts: a voltage-controlled attenuator (VCA) and a programmable gain amplifier (PGA). The PGA output feeds directly into an integrated 2-pole low-pass Butterworth filter.
  • Interfacing the VCA8617 with High-Speed ADCs
    PDF, 72 Kb, Archivo publicado: abr 5, 2005
    The VCA8617 is an 8-channel variable gain amplifier ideally suited for portable and mid-range ultrasound applications. Each channel consists of a Low Noise Amplifier (LNA) and a Variable Gain Amplifier (VGA). The VGA contains two parts: a voltage-controlled attenuator and a programmable gain amplifier. The PGA output feeds directly into an integrated 3-pole low-pass Butterworth filter, which preve
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, Archivo publicado: sept 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, Revisión: A, Archivo publicado: jul 19, 2013
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, Revisión: A, Archivo publicado: mayo 22, 2015
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Archivo publicado: abr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015

Linea modelo

Serie: ADS5271 (2)

Clasificación del fabricante

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)