Datasheet Texas Instruments SN74LVT244BGQNR — Ficha de datos

FabricanteTexas Instruments
SerieSN74LVT244B
Numero de parteSN74LVT244BGQNR
Datasheet Texas Instruments SN74LVT244BGQNR

Hojas de datos

SN74LVT244B datasheet
PDF, 1.4 Mb, Revisión: J, Archivo publicado: sept 9, 2003
Extracto del documento

Precios

Estado

Estado del ciclo de vidaObsoleto (El fabricante ha interrumpido la producción del dispositivo)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin20
Package TypeGQN
Industry STD TermBGA MICROSTAR JUNIOR
JEDEC CodeR-PBGA-N
Width (mm)3
Length (mm)4
Thickness (mm).75
Pitch (mm).65
Max Height (mm)1
Mechanical DataDescargar

Reemplazos

ReplacementSN74LVT244BZQNR
Replacement CodeP

Paramétricos

Approx. Price (US$)0.27 | 1ku
Bits(#)8
F @ Nom Voltage(Max)(Mhz)160
ICC @ Nom Voltage(Max)(mA)0.005
Input TypeTTL/CMOS
Operating Temperature Range(C)-40 to 85
Output Drive (IOL/IOH)(Max)(mA)-32/64
Output TypeLVTTL
Package GroupBGA MICROSTAR JUNIOR
SO
SOIC
SSOP
TSSOP
VQFN
Package Size: mm2:W x L (PKG)20BGA MICROSTAR JUNIOR: 12 mm2: 3 x 4(BGA MICROSTAR JUNIOR)
20VQFN: 16 mm2: 3.5 x 4.5(VQFN)
20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
20SSOP: 56 mm2: 7.8 x 7.2(SSOP)
20SO: 98 mm2: 7.8 x 12.6(SO)
20SOIC: 132 mm2: 10.3 x 12.8(SOIC)
RatingCatalog
Schmitt TriggerNo
Technology FamilyLVT
VCC(Max)(V)3.6
VCC(Min)(V)2.7
Voltage(Nom)(V)3.3
tpd @ Nom Voltage(Max)(ns)3.5

Plan ecológico

RoHSDesobediente
Pb gratisNo

Notas de aplicación

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Archivo publicado: dic 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

Linea modelo

Clasificación del fabricante

  • Semiconductors > Logic > Buffer/Driver/Transceiver > Non-Inverting Buffer/Driver