[ /Title
(CD74H
C4040,
CD74HC
T4040)
/Subject
(High
Speed
CMOS
Logic
12-Stage
Binary CD54HC4040, CD74HC4040,
CD54HCT4040, CD74HCT4040
Data sheet acquired from Harris Semiconductor
SCHS203D High-Speed CMOS Logic
12-Stage Binary Counter February 1998 -Revised October 2003 Features Description Fully Static Operation The ’HC4040 and ’HCT4040 are 14-stage ripple-carry
binary counters. All counter stages are master-slave flipflops. The state of the stage advances one count on the
negative clock transition of each input pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered. Buffered Inputs Common Reset Negative Edge Pulsing Fanout (Over Temperature Range) Ordering Information -Standard Outputs . 10 LSTTL Loads
-Bus Driver Outputs . 15 LSTTL Loads PART NUMBER Wide Operating Temperature Range . -55oC to 125oC TEMP. RANGE
(oC) PACKAGE Balanced Propagation Delay and Transition Times CD54HC4040F3A -55 to 125 16 Ld CERDIP Significant Power Reduction Compared to LSTTL
Logic ICs CD54HCT4040F3A -55 to 125 16 Ld CERDIP CD74HC4040E -55 to 125 16 Ld PDIP CD74HC4040M -55 to 125 16 Ld SOIC CD74HC4040MT -55 to 125 16 Ld SOIC CD74HC4040M96 -55 to 125 16 Ld SOIC CD74HC4040NSR -55 to 125 16 Ld SOP CD74HCT4040E -55 to 125 16 Ld PDIP CD74HCT4040M -55 to 125 16 Ld SOIC CD74HCT4040MT -55 to 125 16 Ld SOIC CD74HCT4040M96 -55 to 125 16 Ld SOIC HC Types …
