Datasheet Texas Instruments THS4271DR — Ficha de datos

FabricanteTexas Instruments
SerieTHS4271
Numero de parteTHS4271DR
Datasheet Texas Instruments THS4271DR

Amplificador de alta velocidad de distorsión ultrarrápida ultrarrápida 8-SOIC -40 a 85

Hojas de datos

Low Noise, High Slew Rate, Unity Gain Stable Voltage Feedback Amplifier datasheet
PDF, 1.7 Mb, Revisión: F, Archivo publicado: oct 16, 2009
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin8
Package TypeD
Industry STD TermSOIC
JEDEC CodeR-PDSO-G
Package QTY2500
CarrierLARGE T&R
Device Marking4271
Width (mm)3.91
Length (mm)4.9
Thickness (mm)1.58
Pitch (mm)1.27
Max Height (mm)1.75
Mechanical DataDescargar

Paramétricos

2nd Harmonic65 dBc
3rd Harmonic80 dBc
@ MHz30
Acl, min spec gain1 V/V
Additional FeaturesN/A
ArchitectureBipolar,Voltage FB
BW @ Acl1400 MHz
CMRR(Min)67 dB
CMRR(Typ)72 dB
GBW(Typ)1400 MHz
Input Bias Current(Max)15000000 pA
Iq per channel(Max)24 mA
Iq per channel(Typ)22 mA
Number of Channels1
Offset Drift(Typ)10 uV/C
Operating Temperature Range-40 to 85 C
Output Current(Typ)160 mA
Package GroupSOIC
Package Size: mm2:W x L8SOIC: 29 mm2: 6 x 4.9(SOIC) PKG
Rail-to-RailNo
RatingCatalog
Slew Rate(Typ)1000 V/us
Total Supply Voltage(Max)10 +5V=5, +/-5V=10
Total Supply Voltage(Min)5 +5V=5, +/-5V=10
Vn at 1kHz(Typ)3 nV/rtHz
Vn at Flatband(Typ)3 nV/rtHz
Vos (Offset Voltage @ 25C)(Max)10 mV

Plan ecológico

RoHSObediente

Kits de diseño y Módulos de evaluación

  • Evaluation Modules & Boards: THS4271EVM
    THS4271 Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • Evaluation Modules & Boards: THS4271EVM-UG
    THS4271 Evaluation Module with Unity Gain
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)

Notas de aplicación

  • Wideband Complementary Current Output DAC Single-Ended Interface
    PDF, 597 Kb, Archivo publicado: jun 21, 2005
    High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
  • Noise Analysis for High Speed Op Amps (Rev. A)
    PDF, 256 Kb, Revisión: A, Archivo publicado: enero 17, 2005
    As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu

Linea modelo

Clasificación del fabricante

  • Semiconductors > Amplifiers > Operational Amplifiers (Op Amps) > High-Speed Op Amps (>=50MHz)