[ /Title
(CD74
HC406
0,
CD74
HCT40
60)
/Subject
(High
Speed
CMOS CD54HC4060, CD74HC4060,
CD54HCT4060, CD74HCT4060
Data sheet acquired from Harris Semiconductor
SCHS207G High-Speed CMOS Logic
14-Stage Binary Counter with Oscillator February 1998 -Revised October 2003 the negative transition of П†I (and П†O). All inputs and outputs
are buffered. Schmitt trigger action on the input-pulse-line
permits unlimited rise and fall times. Features Onboard Oscillator Common Reset In order to achieve a symmetrical waveform in the oscillator
section the HCT4060 input pulse switch points are the same
as in the HC4060; only the MR input in the HCT4060 has
TTL switching levels. Negative-Edge Clocking Fanout (Over Temperature Range)
-Standard Outputs . 10 LSTTL Loads
-Bus Driver Outputs . 15 LSTTL Loads Ordering Information Wide Operating Temperature Range . -55oC to 125oC TEMP. RANGE
(oC) PACKAGE CD54HC4060F3A -55 to 125 16 Ld CERDIP CD54HCT4060F3A -55 to 125 16 Ld CERDIP CD74HC4060E -55 to 125 16 Ld PDIP CD74HC4060M -55 to 125 16 Ld SOIC CD74HC4060MT -55 to 125 16 Ld SOIC CD74HC4060M96 -55 to 125 16 Ld SOIC CD74HC4060PW -55 to 125 16 Ld TSSOP CD74HC4060PWR -55 to 125 16 Ld TSSOP CD74HC4060PWT -55 to 125 16 Ld TSSOP CD74HCT4060E -55 to 125 16 Ld PDIP CD74HCT4060M -55 to 125 16 Ld SOIC CD74HCT4060MT -55 to 125 16 Ld SOIC CD74HCT4060M96 -55 to 125 16 Ld SOIC PART NUMBER Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL …
