Datasheet Texas Instruments THS1041CPWR — Ficha de datos

FabricanteTexas Instruments
SerieTHS1041
Numero de parteTHS1041CPWR
Datasheet Texas Instruments THS1041CPWR

Convertidor analógico a digital (ADC) de 10 bits y 40 MSPS 28-TSSOP 0 a 70

Hojas de datos

10-Bit, 40-MSPS Analog-to-Digital Converter With PGA and Clamp datasheet
PDF, 951 Kb, Revisión: C, Archivo publicado: oct 28, 2004
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin28
Package TypePW
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingTH1041
Width (mm)4.4
Length (mm)9.7
Thickness (mm)1
Pitch (mm).65
Max Height (mm)1.2
Mechanical DataDescargar

Paramétricos

# Input Channels1
Analog Input BW900 MHz
ArchitecturePipeline
DNL(Max)1 +/-LSB
DNL(Typ)0.3 +/-LSB
ENOB9.5 Bits
INL(Max)1.5 +/-LSB
INL(Typ)0.75 +/-LSB
Input BufferNo
Input Range2 Vp-p
InterfaceParallel CMOS
Operating Temperature Range0 to 70 C
Package GroupTSSOP
Package Size: mm2:W x L28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP) PKG
Power Consumption(Typ)103 mW
RatingCatalog
Reference ModeExt,Int
Resolution10 Bits
SFDR70 dB
SINAD60 dB
SNR57 dB
Sample Rate(Max)40 MSPS

Plan ecológico

RoHSObediente

Kits de diseño y Módulos de evaluación

  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200 Low-Cost Portable Power Supply Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)

Notas de aplicación

  • Clamp function of high-speed ADC THS1041
    PDF, 235 Kb, Archivo publicado: oct 10, 2006
  • High-Speed ADC THS1041and FPGA Interface Considerations
    PDF, 130 Kb, Archivo publicado: marzo 15, 2007
    The Texas Instruments THS1041 is a 10-bit, 40-MSPS, high-speed analog-to-digital converter (ADC). For many years because of its low power dissipation and extended life, it has been used in various applications such as programmable gain amplifier and built-in clamp. With recent FPGA development, some application systems have been upgraded with a direct interface of the THS1041 to an FPGA, for examp
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, Archivo publicado: sept 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Archivo publicado: abr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Noise Analysis for High Speed Op Amps (Rev. A)
    PDF, 256 Kb, Revisión: A, Archivo publicado: enero 17, 2005
    As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu

Linea modelo

Clasificación del fabricante

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)