Datasheet Texas Instruments ADS5440IPFP — Ficha de datos

FabricanteTexas Instruments
SerieADS5440
Numero de parteADS5440IPFP
Datasheet Texas Instruments ADS5440IPFP

Convertidor analógico a digital de 13 bits, 210-MSPS (ADC) 80-HTQFP -40 a 85

Hojas de datos

13 Bit 210 MSPS Analog-to-Digital Converter datasheet
PDF, 1.1 Mb, Revisión: A, Archivo publicado: dic 14, 2005
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin80
Package TypePFP
Industry STD TermHTQFP
JEDEC CodeS-PQFP-G
Package QTY96
CarrierJEDEC TRAY (10+1)
Device MarkingADS5440IPFP
Width (mm)12
Length (mm)12
Thickness (mm)1
Pitch (mm).5
Max Height (mm)1.2
Mechanical DataDescargar

Paramétricos

# Input Channels1
Analog Input BW500 MHz
ArchitecturePipeline
DNL(Max)0.4 +/-LSB
DNL(Typ)0.4 +/-LSB
ENOB11.4 Bits
INL(Max)0.9 +/-LSB
INL(Typ)0.9 +/-LSB
Input BufferYes
Input Range2.2 Vp-p
InterfaceParallel LVDS
Operating Temperature Range-40 to 85 C
Package GroupHTQFP
Package Size: mm2:W x L80HTQFP: 196 mm2: 14 x 14(HTQFP) PKG
Power Consumption(Typ)2250 mW
RatingCatalog
Reference ModeInt
Resolution13 Bits
SFDR80 dB
SINAD68 dB
SNR69 dB
Sample Rate(Max)210 MSPS

Plan ecológico

RoHSObediente

Kits de diseño y Módulos de evaluación

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    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • Evaluation Modules & Boards: ADS5474EVM
    ADS5474 14-Bit, 400-MSPS Analog-to-Digital Converter Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • Evaluation Modules & Boards: ADS5463EVM
    ADS5463 12-Bit, 500-MSPS Analog-to-Digital Converter Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)

Notas de aplicación

  • High-Speed Analog-to-Digital Converter Basics
    PDF, 1.1 Mb, Archivo publicado: enero 11, 2012
    The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, Revisión: A, Archivo publicado: mayo 22, 2015
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, Revisión: A, Archivo publicado: jul 19, 2013
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Archivo publicado: abr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015

Linea modelo

Serie: ADS5440 (3)

Clasificación del fabricante

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)