Datasheet Texas Instruments SM32C6711DGDPI20EP — Ficha de datos

 
 

 

 
   
 



SGUS054A -AUGUST 2004 -REVISED SEPTEMBER 2005 D Controlled Baseline
D
D
D
D D D D D L1/L2 Memory Architecture -One Assembly/Test Site, One Fabrication
Site
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree†
Excellent-Price/Performance Floating-Point
Digital Signal Processors (DSPs):
320C67xпЈЄ (C6711, C6711B, C6711C, and
C6711D)
-Eight 32-Bit Instructions/Cycle
-100-,150-,167-,200-,250-MHz Clock Rates
-10-, 6.7-, 6-, 5-, 4-ns Instruction Cycle
Time
-600, 900, 1000, 1200, 1500 MFLOPS …