Datasheet Texas Instruments SN74LV126ADR — Ficha de datos

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Documents SN54LV126A, SN74LV126A
SCES131I – MARCH 1998 – REVISED FEBRUARY 2015 SNx4LV126A Quadruple Bus Buffer Gates With 3-State Outputs
1 Features 3 Description The �LV126A quadruple bus buffer gates are
designed for 2-V to 5.5-V VCC operation. 1 2-V to 5.5-V VCC Operation
Max tpd of 6.5 ns at 5 V
Typical VOLP (Output Ground Bounce) 2.3 V at
VCC = 3.3 V, TA = 25В°C
Ioff Supports Live Insertion, Partial Power Down
Mode, and Back Drive Protection
Support Mixed-Mode Voltage Operation on All
Ports
Latch-Up Performance Exceeds 250 mA per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101) These quadruple bus buffer gates are designed for 2V to 5.5-V VCC operation.
The ’LV126A devices feature independent line drivers …