Datasheet Texas Instruments USBN9604SLB — Ficha de datos

USBN9603,USBN9604 USBN9603 USBN9604 Universal Serial Bus Full Speed Node Controller with
Enhanced DMA Support Literature Number: SNOS528L -May 1998 USBN9603/USBN9604 Universal Serial Bus
Full Speed Node Controller with Enhanced DMA Support
General Description Outstanding Features The USBN9603/4 are integrated, USB Node controllers.
Other than the reset mechanism for the clock generation circuit, these two devices are identical. All references to “the
device” in this document refer to both devices, unless otherwise noted.
The device provides enhanced DMA support with many automatic data handling features. It is compatible with USB
specification versions 1.0 and 1.1, and is an advanced version of the USBN9602. Low EMI, low standby current, 24 MHz oscillator в—Џ Advanced DMA mechanism в—Џ Fully static HALT mode with asynchronous wake-up
for bus powered operation в—Џ 5V or 3.3V operation в—Џ Improved input range 3.3V signal voltage regulator в—Џ All unidirectional FIFOs are 64 bytes et
e The device integrates the required USB transceiver with a
3.3V regulator, a Serial Interface Engine (SIE), USB endpoint (EP) FIFOs, a versatile 8-bit parallel interface, a clock
generator and a MICROWIRE/PLUSв„ў interface. Seven
endpoint pipes are supported: one for the mandatory control endpoint and six to support interrupt, bulk and isochronous endpoints. Each endpoint pipe has a dedicated FIFO,
8 bytes for the control endpoint and 64 bytes for the other
endpoints. The 8-bit parallel interface supports multiplexed
and non-multiplexed style CPU address/data buses. A programmable interrupt output scheme allows device configuration for different interrupt signaling requirements. в—Џ Power-up reset and startup delay counter simplify system design в—Џ Simple programming model controlled by external controller в—Џ Available in two packages
— USBN9603/4SLB: small footprint for new designs
and portable applications
— USBN9603/4-28M: standard package, pin-to-pin
compatible with USBN9602-28M ol в—Џ bs Block Diagram CS RD WR A0/ALE D7-0/AD7-0 INTR MODE1-0
RESET
VCC
GND O Microcontroller Interface 24 MHz …