Datasheet Texas Instruments TLV2553IDW — Ficha de datos

FabricanteTexas Instruments
SerieTLV2553
Numero de parteTLV2553IDW
Datasheet Texas Instruments TLV2553IDW

12 bits, 200 KSPS, 11 canales, baja potencia, salida serie de ADC en serie, con Pwrdwn 20-SOIC -40 a 85

Hojas de datos

TLV2553 12-Bit, 200-KSPS, 11-Channel, Low-Power, Serial ADC datasheet
PDF, 1.2 Mb, Revisión: C, Archivo publicado: jul 9, 2015
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricante

Embalaje

Pin20
Package TypeDW
Industry STD TermSOIC
JEDEC CodeR-PDSO-G
Package QTY25
CarrierTUBE
Device MarkingTLV2553I
Width (mm)7.5
Length (mm)12.8
Thickness (mm)2.35
Pitch (mm)1.27
Max Height (mm)2.65
Mechanical DataDescargar

Paramétricos

# Input Channels11
Analog Voltage AVDD(Max)5.5 V
Analog Voltage AVDD(Min)2.7 V
ArchitectureSAR
Digital Supply(Max)5.5 V
Digital Supply(Min)2.7 V
INL(Max)1 +/-LSB
Input Range(Max)5.5 V
Input TypeSingle-Ended
Integrated FeaturesOscillator
InterfaceSPI
Multi-Channel ConfigurationMultiplexed
Operating Temperature Range-40 to 85 C
Package GroupSOIC
Package Size: mm2:W x L20SOIC: 132 mm2: 10.3 x 12.8(SOIC) PKG
Power Consumption(Typ)2.43 mW
RatingCatalog
Reference ModeExt
Resolution12 Bits
SINAD69.5 dB
SNR69.5 dB
Sample Rate (max)200kSPS SPS
Sample Rate(Max)0.2 MSPS

Plan ecológico

RoHSObediente

Kits de diseño y Módulos de evaluación

  • Evaluation Modules & Boards: TLV2553EVM-PDK
    TLV2553 Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • Evaluation Modules & Boards: 5-6KINTERFACE
    5-6K Interface Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)

Notas de aplicación

  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, Revisión: A, Archivo publicado: nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, Archivo publicado: marzo 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

Linea modelo

Clasificación del fabricante

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)