Datasheet Texas Instruments ADS5562IRGZR — Ficha de datos

FabricanteTexas Instruments
SerieADS5562
Numero de parteADS5562IRGZR
Datasheet Texas Instruments ADS5562IRGZR

Convertidor analógico a digital (ADC) de 16 bits y 80 MSPS 48-VQFN -40 a 85

Hojas de datos

ADS556x 16-Bit, 40 and 80 MSPS ADCs With DDR LVDS and CMOS Outputs datasheet
PDF, 1.7 Mb, Revisión: B, Archivo publicado: enero 13, 2016
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin48
Package TypeRGZ
Industry STD TermVQFN
JEDEC CodeS-PQFP-N
Package QTY2500
CarrierLARGE T&R
Device MarkingAZ5562
Width (mm)7
Length (mm)7
Thickness (mm).9
Pitch (mm).5
Max Height (mm)1
Mechanical DataDescargar

Paramétricos

# Input Channels1
Analog Input BW250 MHz
ArchitecturePipeline
DNL(Max)0.95 +/-LSB
DNL(Typ)0.5 +/-LSB
ENOB13.1 Bits
INL(Max)8.5 +/-LSB
INL(Typ)3 +/-LSB
Input BufferNo
Input Range3.6 Vp-p
InterfaceParallel CMOS,Parallel LVDS
Operating Temperature Range-40 to 85 C
Package GroupVQFN
Package Size: mm2:W x L48VQFN: 49 mm2: 7 x 7(VQFN) PKG
Power Consumption(Typ)865 mW
RatingCatalog
Reference ModeExt,Int
Resolution16 Bits
SFDR85 dB
SINAD80.5 dB
SNR84 dB
Sample Rate(Max)80 MSPS

Plan ecológico

RoHSObediente

Kits de diseño y Módulos de evaluación

  • Evaluation Modules & Boards: ADS5560EVM
    ADS5560 16-Bit, 40-MSPS Analog-to-Digital Converter Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200 Low-Cost Portable Power Supply Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  • Evaluation Modules & Boards: ADS5562EVM
    ADS5562 16-Bit, 80-MSPS Analog-to-Digital Converter Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)

Notas de aplicación

  • QFN Layout Guidelines
    PDF, 1.3 Mb, Archivo publicado: jul 28, 2006
    Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs.
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, Revisión: A, Archivo publicado: mayo 22, 2015
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, Revisión: A, Archivo publicado: jul 19, 2013
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Archivo publicado: abr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015

Linea modelo

Serie: ADS5562 (2)

Clasificación del fabricante

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)