Datasheet Texas Instruments ADS7223SRHBR — Ficha de datos

FabricanteTexas Instruments
SerieADS7223
Numero de parteADS7223SRHBR
Datasheet Texas Instruments ADS7223SRHBR

12 bits 1MSPS 4x2 / 2x2 Muestreo simultáneo SAR ADC 32-VQFN -40 a 125

Hojas de datos

ADSxxx3 Dual, 1-MSPS, 16-, 14-, and 12-Bit, 4Г—2 or 2Г—2 Channel, Simultaneous Sampling Analog-to-Digital Converter datasheet
PDF, 1.4 Mb, Revisión: D, Archivo publicado: sept 2, 2017
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin3232
Package TypeRHBRHB
Industry STD TermVQFNVQFN
JEDEC CodeS-PQFP-NS-PQFP-N
Package QTY30003000
CarrierLARGE T&RLARGE T&R
Device Marking7223ADS
Width (mm)55
Length (mm)55
Thickness (mm).9.9
Pitch (mm).5.5
Max Height (mm)11
Mechanical DataDescargarDescargar

Paramétricos

# Input Channels4
Analog Voltage AVDD(Max)5.5 V
Analog Voltage AVDD(Min)2.7 V
ArchitectureSAR
Digital Supply(Max)5.5 V
Digital Supply(Min)2.3 V
INL(Max)0.5 +/-LSB
Input Range(Max)5.5 V
Input TypeDifferential,Pseudo-Differential
Integrated FeaturesN/A
InterfaceSPI
Multi-Channel ConfigurationMultiplexed,Simultaneous Sampling
Operating Temperature Range-40 to 125 C
Package GroupVQFN
Package Size: mm2:W x L32VQFN: 25 mm2: 5 x 5(VQFN) PKG
Power Consumption(Typ)47.2 mW
RatingCatalog
Reference ModeExt,Int
Resolution12 Bits
SINAD72 dB
SNR73 dB
Sample Rate (max)1MSPS SPS
Sample Rate(Max)1 MSPS
THD(Typ)-86 dB

Plan ecológico

RoHSObediente

Notas de aplicación

  • Using the Sequencer and Pseudo-Differential Features of the ADS8363
    PDF, 161 Kb, Archivo publicado: mayo 21, 2014
  • Interfacing to the ADS8363 Pseudo-Differential Operating Mode
    PDF, 548 Kb, Archivo publicado: agosto 4, 2014
  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, Revisión: A, Archivo publicado: nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, Archivo publicado: marzo 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015

Linea modelo

Serie: ADS7223 (2)

Clasificación del fabricante

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)