Datasheet Texas Instruments CD74HC112PWT — Ficha de datos

FabricanteTexas Instruments
SerieCD74HC112
Numero de parteCD74HC112PWT
Datasheet Texas Instruments CD74HC112PWT

Chanclas JK de alta velocidad CMOS Logic Dual Negative-Edge-Triggered con Set and Reset 16-TSSOP -55 a 125

Hojas de datos

CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 datasheet
PDF, 749 Kb, Revisión: H, Archivo publicado: oct 13, 2003
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin16
Package TypePW
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY250
CarrierSMALL T&R
Device MarkingHJ112
Width (mm)4.4
Length (mm)5
Thickness (mm)1
Pitch (mm).65
Max Height (mm)1.2
Mechanical DataDescargar

Paramétricos

Bits2
F @ Nom Voltage(Max)70 Mhz
ICC @ Nom Voltage(Max)0.04 mA
Output Drive (IOL/IOH)(Max)-6/6 mA
Package GroupTSSOP
Package Size: mm2:W x L16TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG
RatingCatalog
Schmitt TriggerNo
Technology FamilyHC
VCC(Max)6 V
VCC(Min)2 V
Voltage(Nom)3.3,5 V
tpd @ Nom Voltage(Max)53 ns

Plan ecológico

RoHSObediente

Notas de aplicación

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    PDF, 769 Kb, Archivo publicado: sept 7, 2001
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  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, Archivo publicado: abr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
  • SN54/74HCT CMOS Logic Family Applications and Restrictions
    PDF, 102 Kb, Archivo publicado: mayo 1, 1996
    The TI SN54/74HCT family of CMOS devices is a subgroup of the SN74HC series with the HCT circuitry modified to meet the interfacing requirements of TTL outputs to high-speed CMOS inputs. The HCT devices can be driven by the TTL circuits directly without additional components. This document describes the TTL/HC interface the operating voltages circuit noise and power consumption. A Bergeron anal

Linea modelo

Clasificación del fabricante

  • Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop