Datasheet Texas Instruments ADS5240 — Ficha de datos

FabricanteTexas Instruments
SerieADS5240
Datasheet Texas Instruments ADS5240

Convertidor analógico a digital de cuatro canales, 12 bits y 40 MSPS (ADC)

Hojas de datos

4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface (Rev. E)
PDF, 1.2 Mb, Revisión: E, Archivo publicado: enero 6, 2009
4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface datasheet
PDF, 1.2 Mb, Revisión: E, Archivo publicado: enero 6, 2009
Extracto del documento

Precios

Estado

ADS5240IPAPADS5240IPAPG4ADS5240IPAPTADS5240IPAPTG4
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNo

Embalaje

ADS5240IPAPADS5240IPAPG4ADS5240IPAPTADS5240IPAPTG4
N1234
Pin64646464
Package TypePAPPAPPAPPAP
Industry STD TermHTQFPHTQFPHTQFPHTQFP
JEDEC CodeS-PQFP-GS-PQFP-GS-PQFP-GS-PQFP-G
Package QTY160160250250
CarrierJEDEC TRAY (10+1)JEDEC TRAY (10+1)SMALL T&RSMALL T&R
Device MarkingADS5240IPAPADS5240IPAPADS5240IPAPADS5240IPAP
Width (mm)10101010
Length (mm)10101010
Thickness (mm)1111
Pitch (mm).5.5.5.5
Max Height (mm)1.21.21.21.2
Mechanical DataDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsADS5240IPAP
ADS5240IPAP
ADS5240IPAPG4
ADS5240IPAPG4
ADS5240IPAPT
ADS5240IPAPT
ADS5240IPAPTG4
ADS5240IPAPTG4
# Input Channels4444
Analog Input BW, MHz300300
Analog Input BW(MHz)300300
Approx. Price (US$)32.25 | 1ku32.25 | 1ku
ArchitecturePipelinePipelinePipelinePipeline
DNL(Max), +/-LSB0.90.9
DNL(Max)(+/-LSB)0.90.9
DNL(Typ), +/-LSB0.40.4
ENOB, Bits11.311.3
ENOB(Bits)11.311.3
INL(Max), +/-LSB22
INL(Max)(+/-LSB)22
INL(Typ), +/-LSB0.750.75
Input BufferNoNo
Input Range11V (p-p)11V (p-p)
InterfaceParallel LVDSParallel LVDSParallel LVDSParallel LVDS
Operating Temperature Range, C-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85
Package GroupHTQFPHTQFPHTQFPHTQFP
Package Size(mm2=WxL)64HTQFP: 144 mm2: 12 x 1264HTQFP: 144 mm2: 12 x 12
Package Size: mm2:W x L, PKG64HTQFP: 144 mm2: 12 x 12(HTQFP)64HTQFP: 144 mm2: 12 x 12(HTQFP)
Power Consumption(Typ), mW607607
Power Consumption(Typ)(mW)607607
RatingCatalogCatalogCatalogCatalog
Reference ModeExt,IntExt
Int
Ext,IntExt
Int
Resolution, Bits1212
Resolution(Bits)1212
SFDR, dB8585
SFDR(dB)8585
SINAD, dB7070
SINAD(dB)7070
SNR, dB70.570.5
SNR(dB)70.570.5
Sample Rate (max)(SPS)40MSPS40MSPS
Sample Rate(Max), MSPS4040

Plan ecológico

ADS5240IPAPADS5240IPAPG4ADS5240IPAPTADS5240IPAPTG4
RoHSObedienteObedienteObedienteObediente
Pb gratis

Notas de aplicación

  • Interfacing High-Speed LVDS Outputs of the ADS527x/ADS524x
    PDF, 67 Kb, Archivo publicado: feb 23, 2005
    The ADS527x and ADS524x families of devices are high-performance octal/quad channel analog-to-digital converters, ideal for the highest system density. Serial low voltage differential signaling (LVDS) outputs reduce the number of I/O interfaces required, power and overall package size. These device families are rated to work from sampling rates of 20MSPS to 70MSPS, corresponding to data rates of 2
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, Archivo publicado: sept 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, Revisión: A, Archivo publicado: mayo 22, 2015
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, Revisión: A, Archivo publicado: jul 19, 2013
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Archivo publicado: abr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015

Linea modelo

Clasificación del fabricante

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)