Datasheet Texas Instruments ADS5423 — Ficha de datos

FabricanteTexas Instruments
SerieADS5423
Datasheet Texas Instruments ADS5423

Convertidor analógico a digital (ADC) de 14 bits y 80 MSPS

Hojas de datos

ADS5423: 14-Bit 80 MSPS ADC (Rev. A)
PDF, 1.9 Mb, Revisión: A, Archivo publicado: enero 14, 2010
ADS5423: 14-Bit 80 MSPS ADC datasheet
PDF, 1.8 Mb, Revisión: A, Archivo publicado: enero 14, 2010
Extracto del documento

Precios

Estado

ADS5423IPGPADS5423IPGPRADS5423IPJYADS5423IPJYG4ADS5423IPJYRG4
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)
Disponibilidad de muestra del fabricanteNoNoNoNo

Embalaje

ADS5423IPGPADS5423IPGPRADS5423IPJYADS5423IPJYG4ADS5423IPJYRG4
N12345
Pin5252525252
Package TypePGPPGPPJYPJYPJY
Industry STD TermHTQFPHTQFPQFPQFPQFP
JEDEC CodeS-PQFP-GS-PQFP-GS-PQFP-GS-PQFP-GS-PQFP-G
Package QTY1601000
CarrierJEDEC TRAY (10+1)LARGE T&R
Device MarkingADS5423IPGPADS5423IPGPADS5423I
Width (mm)1010101010
Length (mm)1010101010
Thickness (mm)111.41.41.4
Pitch (mm).65.65.65.65.65
Max Height (mm)1.21.21.61.61.6
Mechanical DataDescargarDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsADS5423IPGP
ADS5423IPGP
ADS5423IPGPR
ADS5423IPGPR
ADS5423IPJY
ADS5423IPJY
ADS5423IPJYG4
ADS5423IPJYG4
ADS5423IPJYRG4
ADS5423IPJYRG4
# Input Channels11111
Analog Input BW, MHz570570
Analog Input BW(MHz)570570570
Approx. Price (US$)44.00 | 1ku44.00 | 1ku44.00 | 1ku
ArchitecturePipelinePipelinePipelinePipelinePipeline
DNL(Max), +/-LSB0.50.5
DNL(Max)(+/-LSB)0.50.50.5
DNL(Typ), +/-LSB0.50.5
ENOB, Bits12.212.2
ENOB(Bits)12.212.212.2
INL(Max), +/-LSB1.51.5
INL(Max)(+/-LSB)1.51.51.5
INL(Typ), +/-LSB1.51.5
Input BufferNoNo
Input Range2.22.22.2V (p-p)2.2V (p-p)2.2V (p-p)
InterfaceParallel LVDSParallel LVDSParallel LVDS
Serial SPI Interface
Parallel LVDS
Serial SPI Interface
Parallel LVDS
Serial SPI Interface
Operating Temperature Range, C-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85-40 to 85
Package GroupHTQFPHTQFPHTQFPHTQFPHTQFP
Package Size(mm2=WxL)52HTQFP: 144 mm2: 12 x 1252HTQFP: 144 mm2: 12 x 1252HTQFP: 144 mm2: 12 x 12
Package Size: mm2:W x L, PKG52HTQFP: 144 mm2: 12 x 12(HTQFP)52HTQFP: 144 mm2: 12 x 12(HTQFP)
Power Consumption(Typ), mW18501850
Power Consumption(Typ)(mW)185018501850
RatingCatalogCatalogCatalogCatalogCatalog
Reference ModeIntIntIntIntInt
Resolution, Bits1414
Resolution(Bits)141414
SFDR, dB9393
SFDR(dB)939393
SINAD, dB74.274.2
SINAD(dB)74.274.274.2
SNR, dB74.374.3
SNR(dB)74.374.374.3
Sample Rate (max)(SPS)80MSPS80MSPS80MSPS
Sample Rate(Max), MSPS8080

Plan ecológico

ADS5423IPGPADS5423IPGPRADS5423IPJYADS5423IPJYG4ADS5423IPJYRG4
RoHSObedienteObedienteDesobedienteDesobedienteDesobediente
Pb gratisNoNoNo

Notas de aplicación

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    PDF, 2.0 Mb, Revisión: A, Archivo publicado: mayo 22, 2015
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
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  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
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    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
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    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015
  • Clocking High-Speed Data Converters
    PDF, 310 Kb, Archivo publicado: enero 18, 2005
  • High-Speed, Analog-to-Digital Converter Basics
    PDF, 1.1 Mb, Archivo publicado: enero 11, 2012
    The goal of this document is to introduce a wide range of theories and topics that are relevant to high-speed, analog-to-digital converters (ADC). This document provides details on sampling theory,
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, Revisión: A, Archivo publicado: mayo 22, 2015
    ADS6129, ADS6149 Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, Revisión: A, Archivo publicado: jul 19, 2013
    ADS4149 Why Use Oversampling when Undersampling Can Do the Job?
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Archivo publicado: abr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the refe
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed, high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483, which is capable of
  • Interleaving Analog-to-Digital Converters
    PDF, 64 Kb, Archivo publicado: oct 2, 2000
    It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration s
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    PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015
    AB-082 Principles of Data Acquisition and Conversion
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (ΔΣ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specificati
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    PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015
    AB-084 Analog-to-Digital Grounding Practices Affect System Performance
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    Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its oper

Linea modelo

Clasificación del fabricante

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)