Datasheet Texas Instruments ADS930 — Ficha de datos

FabricanteTexas Instruments
SerieADS930
Datasheet Texas Instruments ADS930

8 bits, 30 MSPS ADC SE / entradas diferidas con referencia interna. y baja potencia, apagado

Hojas de datos

ADS930: SpeedPlus? 8-Bit, 30MHz Sampling Analog-To-Digital Converter datasheet
PDF, 416 Kb, Revisión: A, Archivo publicado: feb 23, 2001
Extracto del documento
ADS930: SpeedPlus? 8-Bit, 30MHz Sampling Analog-To-Digital Converter (Rev. A)
PDF, 416 Kb, Revisión: A, Archivo publicado: feb 23, 2001

Precios

Estado

ADS930EADS930E/1KADS930E/1KG4
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNo

Embalaje

ADS930EADS930E/1KADS930E/1KG4
N123
Pin282828
Package TypeDBDBDB
Industry STD TermSSOPSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY5010001000
CarrierTUBELARGE T&RLARGE T&R
Device MarkingADS930EADS930EADS930E
Width (mm)5.35.35.3
Length (mm)10.210.210.2
Thickness (mm)1.951.951.95
Pitch (mm).65.65.65
Max Height (mm)222
Mechanical DataDescargarDescargarDescargar

Paramétricos

Parameters / ModelsADS930E
ADS930E
ADS930E/1K
ADS930E/1K
ADS930E/1KG4
ADS930E/1KG4
# Input Channels111
Analog Input BW, MHz100100
Analog Input BW(MHz)100
Approx. Price (US$)3.12 | 1ku
ArchitecturePipelinePipelinePipeline
DNL(Max), +/-LSB11
DNL(Max)(+/-LSB)1
DNL(Typ), +/-LSB0.40.4
ENOB, Bits7.17.1
ENOB(Bits)7.1
INL(Max), +/-LSB2.52.5
INL(Max)(+/-LSB)2.5
INL(Typ), +/-LSB11
Input BufferNoNo
Input Range1,21,21V / 2V (p-p)
InterfaceParallel CMOSParallel CMOSParallel CMOS
Operating Temperature Range, C-40 to 85-40 to 85
Package GroupSSOPSSOPSSOP
Package Size(mm2=WxL)28SSOP: 80 mm2: 7.8 x 10.2
Package Size: mm2:W x L, PKG28SSOP: 80 mm2: 7.8 x 10.2(SSOP)28SSOP: 80 mm2: 7.8 x 10.2(SSOP)
Power Consumption(Typ), mW6666
Power Consumption(Typ)(mW)66
RatingCatalogCatalogCatalog
Reference ModeExt,IntExt,IntInt
Ext
Resolution, Bits88
Resolution(Bits)8
SFDR, dB5050
SFDR(dB)50
SINAD, dB4545
SINAD(dB)45
SNR, dB4646
SNR(dB)46
Sample Rate (max)(SPS)30MSPS
Sample Rate(Max), MSPS3030

Plan ecológico

ADS930EADS930E/1KADS930E/1KG4
RoHSObedienteObedienteTBD
Pb gratisNo

Notas de aplicación

  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, Archivo publicado: sept 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Archivo publicado: abr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

Linea modelo

Clasificación del fabricante

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)