Datasheet Texas Instruments CD74AC112 — Ficha de datos
Fabricante | Texas Instruments |
Serie | CD74AC112 |
Chanclas JK de doble filo de borde negativo con ajuste y reinicio
Hojas de datos
CD54AC112, CD74AC112 datasheet
PDF, 857 Kb, Archivo publicado: enero 17, 2003
Extracto del documento
Precios
Estado
CD74AC112E | CD74AC112EE4 | CD74AC112M | CD74AC112M96 | CD74AC112M96G4 | |
---|---|---|---|---|---|
Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) |
Disponibilidad de muestra del fabricante | No | No | No | No | No |
Embalaje
CD74AC112E | CD74AC112EE4 | CD74AC112M | CD74AC112M96 | CD74AC112M96G4 | |
---|---|---|---|---|---|
N | 1 | 2 | 3 | 4 | 5 |
Pin | 16 | 16 | 16 | 16 | 16 |
Package Type | N | N | D | D | D |
Industry STD Term | PDIP | PDIP | SOIC | SOIC | SOIC |
JEDEC Code | R-PDIP-T | R-PDIP-T | R-PDSO-G | R-PDSO-G | R-PDSO-G |
Package QTY | 25 | 25 | 40 | 2500 | |
Carrier | TUBE | TUBE | TUBE | LARGE T&R | |
Device Marking | CD74AC112E | CD74AC112E | AC112M | AC112M | |
Width (mm) | 6.35 | 6.35 | 3.91 | 3.91 | 3.91 |
Length (mm) | 19.3 | 19.3 | 9.9 | 9.9 | 9.9 |
Thickness (mm) | 3.9 | 3.9 | 1.58 | 1.58 | 1.58 |
Pitch (mm) | 2.54 | 2.54 | 1.27 | 1.27 | 1.27 |
Max Height (mm) | 5.08 | 5.08 | 1.75 | 1.75 | 1.75 |
Mechanical Data | Descargar | Descargar | Descargar | Descargar | Descargar |
Paramétricos
Parameters / Models | CD74AC112E | CD74AC112EE4 | CD74AC112M | CD74AC112M96 | CD74AC112M96G4 |
---|---|---|---|---|---|
Approx. Price (US$) | 0.19 | 1ku | ||||
Bits | 2 | 2 | 2 | 2 | |
Bits(#) | 2 | ||||
F @ Nom Voltage(Max), Mhz | 100 | 100 | 100 | 100 | |
F @ Nom Voltage(Max)(Mhz) | 100 | ||||
ICC @ Nom Voltage(Max), mA | 0.04 | 0.04 | 0.04 | 0.04 | |
ICC @ Nom Voltage(Max)(mA) | 0.04 | ||||
Output Drive (IOL/IOH)(Max), mA | -24/24 | -24/24 | -24/24 | -24/24 | |
Output Drive (IOL/IOH)(Max)(mA) | -24/24 | ||||
Package Group | PDIP | PDIP | SOIC | SOIC | SOIC |
Package Size: mm2:W x L, PKG | See datasheet (PDIP) | See datasheet (PDIP) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | |
Package Size: mm2:W x L (PKG) | See datasheet (PDIP) | ||||
Rating | Catalog | Catalog | Catalog | Catalog | Catalog |
Schmitt Trigger | No | No | No | No | No |
Technology Family | AC | AC | AC | AC | AC |
VCC(Max), V | 5.5 | 5.5 | 5.5 | 5.5 | |
VCC(Max)(V) | 5.5 | ||||
VCC(Min), V | 1.5 | 1.5 | 1.5 | 1.5 | |
VCC(Min)(V) | 1.5 | ||||
Voltage(Nom), V | 3.3,5 | 3.3,5 | 3.3,5 | 3.3,5 | |
Voltage(Nom)(V) | 3.3 5 | ||||
tpd @ Nom Voltage(Max), ns | 11.1 | 11.1 | 11.1 | 11.1 | |
tpd @ Nom Voltage(Max)(ns) | 11.1 |
Plan ecológico
CD74AC112E | CD74AC112EE4 | CD74AC112M | CD74AC112M96 | CD74AC112M96G4 | |
---|---|---|---|---|---|
RoHS | Obediente | Obediente | Obediente | Obediente | Desobediente |
Pb gratis | No | Sí | Sí |
Notas de aplicación
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revisión: A, Archivo publicado: feb 6, 2015
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, Archivo publicado: abr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
Linea modelo
Serie: CD74AC112 (5)
Clasificación del fabricante
- Semiconductors> Logic> Flip-Flop/Latch/Register> J-K Flip-Flop