Datasheet Texas Instruments CD74AC112 — Ficha de datos

FabricanteTexas Instruments
SerieCD74AC112
Datasheet Texas Instruments CD74AC112

Chanclas JK de doble filo de borde negativo con ajuste y reinicio

Hojas de datos

CD54AC112, CD74AC112 datasheet
PDF, 857 Kb, Archivo publicado: enero 17, 2003
Extracto del documento

Precios

Estado

CD74AC112ECD74AC112EE4CD74AC112MCD74AC112M96CD74AC112M96G4
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNoNo

Embalaje

CD74AC112ECD74AC112EE4CD74AC112MCD74AC112M96CD74AC112M96G4
N12345
Pin1616161616
Package TypeNNDDD
Industry STD TermPDIPPDIPSOICSOICSOIC
JEDEC CodeR-PDIP-TR-PDIP-TR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY2525402500
CarrierTUBETUBETUBELARGE T&R
Device MarkingCD74AC112ECD74AC112EAC112MAC112M
Width (mm)6.356.353.913.913.91
Length (mm)19.319.39.99.99.9
Thickness (mm)3.93.91.581.581.58
Pitch (mm)2.542.541.271.271.27
Max Height (mm)5.085.081.751.751.75
Mechanical DataDescargarDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsCD74AC112E
CD74AC112E
CD74AC112EE4
CD74AC112EE4
CD74AC112M
CD74AC112M
CD74AC112M96
CD74AC112M96
CD74AC112M96G4
CD74AC112M96G4
Approx. Price (US$)0.19 | 1ku
Bits2222
Bits(#)2
F @ Nom Voltage(Max), Mhz100100100100
F @ Nom Voltage(Max)(Mhz)100
ICC @ Nom Voltage(Max), mA0.040.040.040.04
ICC @ Nom Voltage(Max)(mA)0.04
Output Drive (IOL/IOH)(Max), mA-24/24-24/24-24/24-24/24
Output Drive (IOL/IOH)(Max)(mA)-24/24
Package GroupPDIPPDIPSOICSOICSOIC
Package Size: mm2:W x L, PKGSee datasheet (PDIP)See datasheet (PDIP)16SOIC: 59 mm2: 6 x 9.9(SOIC)16SOIC: 59 mm2: 6 x 9.9(SOIC)
Package Size: mm2:W x L (PKG)See datasheet (PDIP)
RatingCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNo
Technology FamilyACACACACAC
VCC(Max), V5.55.55.55.5
VCC(Max)(V)5.5
VCC(Min), V1.51.51.51.5
VCC(Min)(V)1.5
Voltage(Nom), V3.3,53.3,53.3,53.3,5
Voltage(Nom)(V)3.3
5
tpd @ Nom Voltage(Max), ns11.111.111.111.1
tpd @ Nom Voltage(Max)(ns)11.1

Plan ecológico

CD74AC112ECD74AC112EE4CD74AC112MCD74AC112M96CD74AC112M96G4
RoHSObedienteObedienteObedienteObedienteDesobediente
Pb gratisNo

Notas de aplicación

  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revisión: A, Archivo publicado: feb 6, 2015
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, Archivo publicado: abr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Linea modelo

Clasificación del fabricante

  • Semiconductors> Logic> Flip-Flop/Latch/Register> J-K Flip-Flop