Datasheet Texas Instruments CD74AC20 — Ficha de datos

FabricanteTexas Instruments
SerieCD74AC20
Datasheet Texas Instruments CD74AC20

Puertas dobles NAND de 4 entradas

Hojas de datos

CD74AC20 datasheet
PDF, 594 Kb, Revisión: B, Archivo publicado: nov 15, 2002
Extracto del documento

Precios

Estado

CD74AC20ECD74AC20MCD74AC20M96CD74AC20M96E4CD74AC20M96G4CD74AC20MG4
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNoNoNo

Embalaje

CD74AC20ECD74AC20MCD74AC20M96CD74AC20M96E4CD74AC20M96G4CD74AC20MG4
N123456
Pin141414141414
Package TypeNDDDDD
Industry STD TermPDIPSOICSOICSOICSOICSOIC
JEDEC CodeR-PDIP-TR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY255025002500250050
CarrierTUBETUBELARGE T&RLARGE T&RLARGE T&RTUBE
Device MarkingCD74AC20EAC20MAC20MAC20MAC20MAC20M
Width (mm)6.353.913.913.913.913.91
Length (mm)19.38.658.658.658.658.65
Thickness (mm)3.91.581.581.581.581.58
Pitch (mm)2.541.271.271.271.271.27
Max Height (mm)5.081.751.751.751.751.75
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsCD74AC20E
CD74AC20E
CD74AC20M
CD74AC20M
CD74AC20M96
CD74AC20M96
CD74AC20M96E4
CD74AC20M96E4
CD74AC20M96G4
CD74AC20M96G4
CD74AC20MG4
CD74AC20MG4
Bits222222
F @ Nom Voltage(Max), Mhz100100100100100100
ICC @ Nom Voltage(Max), mA0.040.040.040.040.040.04
Operating Temperature Range, C-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125
Output Drive (IOL/IOH)(Max), mA24/-2424/-2424/-2424/-2424/-2424/-24
Package GroupPDIPSOICSOICSOICSOICSOIC
Package Size: mm2:W x L, PKGSee datasheet (PDIP)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)
RatingCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNo
Technology FamilyACACACACACAC
VCC(Max), V5.55.55.55.55.55.5
VCC(Min), V1.51.51.51.51.51.5
Voltage(Nom), V1.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,5
tpd @ Nom Voltage(Max), ns139,15.5,11.1139,15.5,11.1139,15.5,11.1139,15.5,11.1139,15.5,11.1139,15.5,11.1

Plan ecológico

CD74AC20ECD74AC20MCD74AC20M96CD74AC20M96E4CD74AC20M96G4CD74AC20MG4
RoHSObedienteObedienteObedienteObedienteObedienteObediente
Pb gratis

Notas de aplicación

  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, Archivo publicado: abr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Linea modelo

Clasificación del fabricante

  • Semiconductors> Logic> Gate> NAND Gate