Datasheet Texas Instruments CD74ACT00 — Ficha de datos

FabricanteTexas Instruments
SerieCD74ACT00
Datasheet Texas Instruments CD74ACT00

Puertas NAND Quad de 2 entradas

Hojas de datos

Quadruple 2-Input Positive-NAND Gates datasheet
PDF, 969 Kb, Revisión: B, Archivo publicado: jun 12, 2002
Extracto del documento

Precios

Estado

CD74ACT00ECD74ACT00EE4CD74ACT00MCD74ACT00M96CD74ACT00M96E4CD74ACT00ME4CD74ACT00MG4
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNoNoNoNo

Embalaje

CD74ACT00ECD74ACT00EE4CD74ACT00MCD74ACT00M96CD74ACT00M96E4CD74ACT00ME4CD74ACT00MG4
N1234567
Pin14141414141414
Package TypeNNDDDDD
Industry STD TermPDIPPDIPSOICSOICSOICSOICSOIC
JEDEC CodeR-PDIP-TR-PDIP-TR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY252550250025005050
CarrierTUBETUBETUBELARGE T&RLARGE T&RTUBETUBE
Device MarkingCD74ACT00ECD74ACT00EACT00MACT00MACT00MACT00MACT00M
Width (mm)6.356.353.913.913.913.913.91
Length (mm)19.319.38.658.658.658.658.65
Thickness (mm)3.93.91.581.581.581.581.58
Pitch (mm)2.542.541.271.271.271.271.27
Max Height (mm)5.085.081.751.751.751.751.75
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsCD74ACT00E
CD74ACT00E
CD74ACT00EE4
CD74ACT00EE4
CD74ACT00M
CD74ACT00M
CD74ACT00M96
CD74ACT00M96
CD74ACT00M96E4
CD74ACT00M96E4
CD74ACT00ME4
CD74ACT00ME4
CD74ACT00MG4
CD74ACT00MG4
Bits4444444
F @ Nom Voltage(Max), Mhz90909090909090
ICC @ Nom Voltage(Max), mA0.040.040.040.040.040.040.04
Operating Temperature Range, C-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125
Output Drive (IOL/IOH)(Max), mA24/-2424/-2424/-2424/-2424/-2424/-2424/-24
Package GroupPDIPPDIPSOICSOICSOICSOICSOIC
Package Size: mm2:W x L, PKGSee datasheet (PDIP)See datasheet (PDIP)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNo
Technology FamilyACTACTACTACTACTACTACT
VCC(Max), V5.55.55.55.55.55.55.5
VCC(Min), V4.54.54.54.54.54.54.5
Voltage(Nom), V5555555
tpd @ Nom Voltage(Max), ns9.59.59.59.59.59.59.5

Plan ecológico

CD74ACT00ECD74ACT00EE4CD74ACT00MCD74ACT00M96CD74ACT00M96E4CD74ACT00ME4CD74ACT00MG4
RoHSObedienteObedienteObedienteObedienteObedienteObedienteObediente
Pb gratis

Notas de aplicación

  • Selecting the Right Level Translation Solution (Rev. A)
    PDF, 313 Kb, Revisión: A, Archivo publicado: jun 22, 2004
    Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, Archivo publicado: abr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Linea modelo

Clasificación del fabricante

  • Semiconductors> Logic> Gate> NAND Gate