Datasheet Texas Instruments CD74ACT112 — Ficha de datos

FabricanteTexas Instruments
SerieCD74ACT112
Datasheet Texas Instruments CD74ACT112

Chanclas JK disparadas de borde negativo doble con configuración y restablecimiento

Hojas de datos

CD54ACT112, CD74ACT112 datasheet
PDF, 796 Kb, Archivo publicado: enero 17, 2003
Extracto del documento

Precios

Estado

CD74ACT112MCD74ACT112M96CD74ACT112ME4CD74ACT112MG4
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNo

Embalaje

CD74ACT112MCD74ACT112M96CD74ACT112ME4CD74ACT112MG4
N1234
Pin16161616
Package TypeDDDD
Industry STD TermSOICSOICSOICSOIC
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY4025004040
CarrierTUBELARGE T&RTUBETUBE
Device MarkingACT112MACT112MACT112MACT112M
Width (mm)3.913.913.913.91
Length (mm)9.99.99.99.9
Thickness (mm)1.581.581.581.58
Pitch (mm)1.271.271.271.27
Max Height (mm)1.751.751.751.75
Mechanical DataDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsCD74ACT112M
CD74ACT112M
CD74ACT112M96
CD74ACT112M96
CD74ACT112ME4
CD74ACT112ME4
CD74ACT112MG4
CD74ACT112MG4
Bits2222
F @ Nom Voltage(Max), Mhz90909090
ICC @ Nom Voltage(Max), mA0.040.040.040.04
Output Drive (IOL/IOH)(Max), mA-24/24-24/24-24/24-24/24
Package GroupSOICSOICSOICSOIC
Package Size: mm2:W x L, PKG16SOIC: 59 mm2: 6 x 9.9(SOIC)16SOIC: 59 mm2: 6 x 9.9(SOIC)16SOIC: 59 mm2: 6 x 9.9(SOIC)16SOIC: 59 mm2: 6 x 9.9(SOIC)
RatingCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNo
Technology FamilyACTACTACTACT
VCC(Max), V5.55.55.55.5
VCC(Min), V4.54.54.54.5
Voltage(Nom), V5555
tpd @ Nom Voltage(Max), ns11.111.111.111.1

Plan ecológico

CD74ACT112MCD74ACT112M96CD74ACT112ME4CD74ACT112MG4
RoHSObedienteObedienteObedienteObediente

Notas de aplicación

  • Selecting the Right Level Translation Solution (Rev. A)
    PDF, 313 Kb, Revisión: A, Archivo publicado: jun 22, 2004
    Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revisión: A, Archivo publicado: feb 6, 2015
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, Archivo publicado: abr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Linea modelo

Clasificación del fabricante

  • Semiconductors> Logic> Flip-Flop/Latch/Register> J-K Flip-Flop