Datasheet Texas Instruments CD74ACT112 — Ficha de datos
Fabricante | Texas Instruments |
Serie | CD74ACT112 |
Chanclas JK disparadas de borde negativo doble con configuración y restablecimiento
Hojas de datos
CD54ACT112, CD74ACT112 datasheet
PDF, 796 Kb, Archivo publicado: enero 17, 2003
Extracto del documento
Precios
Estado
CD74ACT112M | CD74ACT112M96 | CD74ACT112ME4 | CD74ACT112MG4 | |
---|---|---|---|---|
Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) |
Disponibilidad de muestra del fabricante | No | No | No | No |
Embalaje
CD74ACT112M | CD74ACT112M96 | CD74ACT112ME4 | CD74ACT112MG4 | |
---|---|---|---|---|
N | 1 | 2 | 3 | 4 |
Pin | 16 | 16 | 16 | 16 |
Package Type | D | D | D | D |
Industry STD Term | SOIC | SOIC | SOIC | SOIC |
JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
Package QTY | 40 | 2500 | 40 | 40 |
Carrier | TUBE | LARGE T&R | TUBE | TUBE |
Device Marking | ACT112M | ACT112M | ACT112M | ACT112M |
Width (mm) | 3.91 | 3.91 | 3.91 | 3.91 |
Length (mm) | 9.9 | 9.9 | 9.9 | 9.9 |
Thickness (mm) | 1.58 | 1.58 | 1.58 | 1.58 |
Pitch (mm) | 1.27 | 1.27 | 1.27 | 1.27 |
Max Height (mm) | 1.75 | 1.75 | 1.75 | 1.75 |
Mechanical Data | Descargar | Descargar | Descargar | Descargar |
Paramétricos
Parameters / Models | CD74ACT112M | CD74ACT112M96 | CD74ACT112ME4 | CD74ACT112MG4 |
---|---|---|---|---|
Bits | 2 | 2 | 2 | 2 |
F @ Nom Voltage(Max), Mhz | 90 | 90 | 90 | 90 |
ICC @ Nom Voltage(Max), mA | 0.04 | 0.04 | 0.04 | 0.04 |
Output Drive (IOL/IOH)(Max), mA | -24/24 | -24/24 | -24/24 | -24/24 |
Package Group | SOIC | SOIC | SOIC | SOIC |
Package Size: mm2:W x L, PKG | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) |
Rating | Catalog | Catalog | Catalog | Catalog |
Schmitt Trigger | No | No | No | No |
Technology Family | ACT | ACT | ACT | ACT |
VCC(Max), V | 5.5 | 5.5 | 5.5 | 5.5 |
VCC(Min), V | 4.5 | 4.5 | 4.5 | 4.5 |
Voltage(Nom), V | 5 | 5 | 5 | 5 |
tpd @ Nom Voltage(Max), ns | 11.1 | 11.1 | 11.1 | 11.1 |
Plan ecológico
CD74ACT112M | CD74ACT112M96 | CD74ACT112ME4 | CD74ACT112MG4 | |
---|---|---|---|---|
RoHS | Obediente | Obediente | Obediente | Obediente |
Notas de aplicación
- Selecting the Right Level Translation Solution (Rev. A)PDF, 313 Kb, Revisión: A, Archivo publicado: jun 22, 2004
Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati - Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revisión: A, Archivo publicado: feb 6, 2015
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, Archivo publicado: abr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
Linea modelo
Serie: CD74ACT112 (4)
Clasificación del fabricante
- Semiconductors> Logic> Flip-Flop/Latch/Register> J-K Flip-Flop