Datasheet Texas Instruments CDC111FN — Ficha de datos

Fabricante	Texas Instruments
Serie	CDC111
Numero de parte	CDC111FN

Controlador de reloj diferencial LVPECL de 3.3V 28-PLCC

Hojas de datos

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PDF, 417 Kb, Revisión: G, Archivo publicado: agosto 28, 1999

Extracto del documento

Estado

Estado del ciclo de vida	Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricante	Sí

Embalaje

Pin	28
Package Type	FN
Industry STD Term	PLCC
JEDEC Code	S-PQCC-J
Package QTY	37
Carrier	TUBE
Device Marking	CDC111FN
Width (mm)	11.51
Length (mm)	11.51
Thickness (mm)	4.06
Pitch (mm)	1.27
Max Height (mm)	4.57
Mechanical Data	Descargar

Paramétricos

Input Frequency(Max)	500 MHz
Input Level	LVPECL
Number of Outputs	9
Output Frequency(Max)	500 MHz
Output Level	LVPECL
Package Group	PLCC
Package Size: mm2:W x L	28PLCC: 132 mm2: 11.51 x 11.51(PLCC) PKG
Rating	Catalog
VCC	3.3 V
VCC Out	3.3 V

Plan ecológico

RoHS

Obediente

Notas de aplicación

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Using TI's CDC111/CDCVF111 W/ TLK3104SA Serial Transceiver for Gigabit Ethernet
PDF, 79 Kb, Archivo publicado: oct 31, 2001
This application report discusses jitter transfer of TI's CDC111/CDCVF111 clock drivers when driving TI's TLK3104 serial gigabit transceiver. This report summarizes worst case peak-to-peak and RMS jitter measurements taken at various points, as indicated in Figures 1 and 2. Two different clock sources are used to provide the reference clock signal for the clock drivers, and the output of each cloc
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Jitter Performance of TI's CDC111/CDCVF111
PDF, 149 Kb, Archivo publicado: oct 29, 2001
This application report discusses various jitter measurements of TI?s CDC111/CDCVF111 while being driven by three different clock sources (VCXOs). The data contained in this report shows that the CDC111/CDCVF111 does not add more than 3 ps of peak-to-peak jitter. Hence, the CDC111 and CDCVF111 are ideal for various SONET and Gigabit Ethernet applications where skew and jitter are of major concern.
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Output Jitter of CDC111/CDCVF111 in ASIC Networking Application
PDF, 361 Kb, Archivo publicado: nov 2, 2001
This report contains a number of peak-to-peak and cycle-to-cycle jitter measurements of TI?s CDC111 and CDCVF111 clock driver. In this ASIC event, both the CDC111/CDCVF111 clock drivers are used as a master clock distribution for the Gandalf Macro Family Testchip. Comprehensive jitter data as well as output signal levels were taken and thus are included for completeness.
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DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
PDF, 135 Kb, Archivo publicado: feb 19, 2003
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AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
PDF, 417 Kb, Revisión: C, Archivo publicado: oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

Linea modelo

Serie: CDC111 (1)

CDC111FN

Clasificación del fabricante

Semiconductors > Clock and Timing > Clock Buffers > Differential