Datasheet Texas Instruments CDC536DB — Ficha de datos

FabricanteTexas Instruments
SerieCDC536
Numero de parteCDC536DB
Datasheet Texas Instruments CDC536DB

Controlador de reloj PLL de 3.3V con opciones de frecuencia 1 / 2x, 1x y 2x 28-SSOP

Hojas de datos

CDC536: 3.3-V PLL Clock Driver With 3-State Outputs datasheet
PDF, 322 Kb, Revisión: G, Archivo publicado: jul 8, 2004
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricante

Embalaje

Pin28
Package TypeDB
Industry STD TermSSOP
JEDEC CodeR-PDSO-G
Package QTY50
CarrierTUBE
Device MarkingCDC536
Width (mm)5.3
Length (mm)10.2
Thickness (mm)1.95
Pitch (mm).65
Max Height (mm)2
Mechanical DataDescargar

Paramétricos

Absolute Jitter (Peak-to-Peak Cycle or Period Jitter)200 ps
Number of Outputs6
Operating Frequency Range(Max)100 MHz
Operating Frequency Range(Min)25 MHz
Package GroupSSOP
Package Size: mm2:W x L28SSOP: 80 mm2: 7.8 x 10.2(SSOP) PKG
RatingCatalog
VCC3.3 V
t(phase error)500 ps
tsk(o)500 ps

Plan ecológico

RoHSObediente

Notas de aplicación

  • Application and Design Considerations for CDC5xx Phase-Lock Loop Clock Drivers
    PDF, 101 Kb, Archivo publicado: abr 1, 1996
    Today?s high-speed system designs require stringent propagation and skew parameters to maintain desired system performance. TI developed the CDC5XX platform of PLL clock drivers to meet the need for high-performance clock system components. This document describes the features and functions of the CDC5XX and discusses design considerations and configurations for the CDC586, CDC582, and CDC2582 clo

Linea modelo

Clasificación del fabricante

  • Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers