Datasheet Texas Instruments CDC582PAH — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | CDC582 |
| Numero de parte | CDC582PAH |
Controlador de reloj PLL de 3.3V con salida LVPECL y salidas LVTTL con opciones de frecuencia 1 / 2x, 1x y 2x 52-TQFP
Hojas de datos
3.3-V Phase-Lock Loop Clock Driver With Differential LVPECL Clock Inputs datasheet
PDF, 150 Kb, Revisión: B, Archivo publicado: feb 1, 1996
Extracto del documento
Estado
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | Sí |
Embalaje
| Pin | 52 |
| Package Type | PAH |
| Industry STD Term | TQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 160 |
| Carrier | JEDEC TRAY (10+1) |
| Device Marking | CDC582 |
| Width (mm) | 10 |
| Length (mm) | 10 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Descargar |
Paramétricos
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | 200 ps |
| Number of Outputs | 12 |
| Operating Frequency Range(Max) | 100 MHz |
| Operating Frequency Range(Min) | 25 MHz |
| Package Group | TQFP |
| Package Size: mm2:W x L | 52TQFP: 144 mm2: 12 x 12(TQFP) PKG |
| Rating | Catalog |
| VCC | 3.3 V |
| t(phase error) | 500 ps |
| tsk(o) | 500 ps |
Plan ecológico
| RoHS | Obediente |
Notas de aplicación
- Application and Design Considerations for CDC5xx Phase-Lock Loop Clock DriversPDF, 101 Kb, Archivo publicado: abr 1, 1996
Today?s high-speed system designs require stringent propagation and skew parameters to maintain desired system performance. TI developed the CDC5XX platform of PLL clock drivers to meet the need for high-performance clock system components. This document describes the features and functions of the CDC5XX and discusses design considerations and configurations for the CDC586, CDC582, and CDC2582 clo
Linea modelo
Serie: CDC582 (2)
- CDC582PAH CDC582PAHG4
Clasificación del fabricante
- Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers