Datasheet Texas Instruments CDCE937QPWRQ1 — Ficha de datos

FabricanteTexas Instruments
SerieCDCE937-Q1
Numero de parteCDCE937QPWRQ1
Datasheet Texas Instruments CDCE937QPWRQ1

Catálogo automotriz Sintetizador de reloj VCXO programable de 3 PLL con salidas LVCMOS de 2.5 V o 3.3 V 20-TSSOP -40 a 125

Hojas de datos

CDCEx937-Q1 Programmable 3-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V LVCMOS Outputs datasheet
PDF, 1.5 Mb, Revisión: C, Archivo publicado: dic 16, 2016
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricante

Embalaje

Pin20
Package TypePW
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingCDCE937Q
Width (mm)4.4
Length (mm)6.5
Thickness (mm)1
Pitch (mm).65
Max Height (mm)1.2
Mechanical DataDescargar

Paramétricos

Operating Temperature Range-40 to 125 C
Package GroupTSSOP
Package Size: mm2:W x L20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) PKG

Plan ecológico

RoHSObediente

Notas de aplicación

  • Crystal or Crystal Oscillator Replacement with Silicon Devices
    PDF, 894 Kb, Archivo publicado: jun 18, 2014
    This application report is a general guide that outlines the advantages of using silicon-based timingdevices from Texas Instruments to generate system clocking solutions. This report covers theconventional way to derive system clocks using crystals and crystal oscillators, disadvantages of usingthese mechanical components, and details on replacing them with silicon-based timing devices from
  • General I2C / EEPROM usage for the CDCE(L)9xx family
    PDF, 40 Kb, Archivo publicado: enero 26, 2010
  • VCXO Application Guideline for CDCE(L)9xx Family (Rev. A)
    PDF, 107 Kb, Revisión: A, Archivo publicado: abr 23, 2012
  • Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913
    PDF, 297 Kb, Archivo publicado: sept 23, 2009
    This document presents a method to smoothly change frequency by IВІCв„ў protocol on Texas Instruments CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 Clock Synthesizers, thus avoiding unnecessary intermediate frequencies. It also includes a code example to generate the IВІC protocol for the CDCE(L)9xx with the TMS320C645x.
  • Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency
    PDF, 860 Kb, Archivo publicado: marzo 31, 2008
    Generating a high-frequency system clock Fs (128fs to 768fs) from a low-frequency sampling clock fs (10 kHz to 200 kHz) is challenging, while attempting to maintain low phase jitter. A traditional phase-lock loop (PLL) can do the frequency translation, but the added phase jitter prevents the generated system clock signal from effectively driving high-performance audio data converters. This applica
  • Troubleshooting I2C Bus Protocol
    PDF, 184 Kb, Archivo publicado: oct 19, 2009
    When using the I2Cв„ў bus protocol, the designer must ensure that the hardware complies with the I2C standard. This application report describes the I2C protocol and provides guidelines on debugging a missing acknowledgment, selecting the pullup resistors, or meeting the maximum capacitance load of an I2C bus. A conflict occurs if devices sharing the I2C bus have the same slave address. This

Linea modelo

Serie: CDCE937-Q1 (1)
  • CDCE937QPWRQ1

Clasificación del fabricante

  • Semiconductors > Staging > Unknown > Automotive Clocks