Datasheet Texas Instruments CDCE949 — Ficha de datos

FabricanteTexas Instruments
SerieCDCE949
Datasheet Texas Instruments CDCE949

Sintetizador de reloj VCXO programable de 4 PLL con salidas LVCMOS de 2.5V o 3.3V

Hojas de datos

CDCE(L)913: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction datasheet
PDF, 1.5 Mb, Revisión: F, Archivo publicado: oct 27, 2016
Extracto del documento

Precios

Estado

CDCE949PWCDCE949PWG4CDCE949PWRCDCE949PWRG4
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNo

Embalaje

CDCE949PWCDCE949PWG4CDCE949PWRCDCE949PWRG4
N1234
Pin24242424
Package TypePWPWPWPW
Industry STD TermTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY606020002000
CarrierTUBETUBELARGE T&RLARGE T&R
Device MarkingCDCE949CDCE949CDCE949CDCE949
Width (mm)4.44.44.44.4
Length (mm)7.87.87.87.8
Thickness (mm)1111
Pitch (mm).65.65.65.65
Max Height (mm)1.21.21.21.2
Mechanical DataDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsCDCE949PW
CDCE949PW
CDCE949PWG4
CDCE949PWG4
CDCE949PWR
CDCE949PWR
CDCE949PWRG4
CDCE949PWRG4
Divider RatioUniversalUniversalUniversalUniversal
FunctionClock SynthesizerClock SynthesizerClock SynthesizerClock Synthesizer
Input LevelCrystal,LVCMOSCrystal,LVCMOSCrystal,LVCMOSCrystal,LVCMOS
Jitter-Peak to Peak(P-P) or Cycle to Cycle, C-C60 ps60 ps60 ps60 ps
Number of Outputs9999
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85
Output Frequency(Max), MHz230230230230
Output LevelLVCMOSLVCMOSLVCMOSLVCMOS
Output Skew, ps150150150150
Package GroupTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
ProgrammabilityEEPROMEEPROMEEPROMEEPROM
RatingCatalogCatalogCatalogCatalog
Special FeaturesIntegrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)
VCC, V1.81.81.81.8
VCC Core, V1.81.81.81.8
VCC Out, V2.5,3.32.5,3.32.5,3.32.5,3.3

Plan ecológico

CDCE949PWCDCE949PWG4CDCE949PWRCDCE949PWRG4
RoHSObedienteObedienteObedienteObediente

Notas de aplicación

  • Clocking Recommendations for DM6446 Digital Video EVM with Sngle PLL (Rev. A)
    PDF, 94 Kb, Revisión: A, Archivo publicado: agosto 8, 2007
    The DM6446 (DaVinciв„ў) Digital Video Evaluation Module (EVM) requires a number of clock frequencies to run the system properly. The current clocking proposal of this EVM consists of a VCXO chip PI6CX100-27W, a PLL chip PLL1705, several voltage level translators, and a few oscillators or crystals. This application report discusses an optimized clocking proposal with Texas Instruments new clock driv
  • General I2C / EEPROM usage for the CDCE(L)9xx family
    PDF, 40 Kb, Archivo publicado: enero 26, 2010
  • VCXO Application Guideline for CDCE(L)9xx Family (Rev. A)
    PDF, 107 Kb, Revisión: A, Archivo publicado: abr 23, 2012
  • Practical consideration on choosing a crystal for CDCE(L)9xx family
    PDF, 60 Kb, Archivo publicado: marzo 24, 2008
  • Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913
    PDF, 297 Kb, Archivo publicado: sept 23, 2009
    This document presents a method to smoothly change frequency by IВІCв„ў protocol on Texas Instruments CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 Clock Synthesizers, thus avoiding unnecessary intermediate frequencies. It also includes a code example to generate the IВІC protocol for the CDCE(L)9xx with the TMS320C645x.
  • Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency
    PDF, 860 Kb, Archivo publicado: marzo 31, 2008
    Generating a high-frequency system clock Fs (128fs to 768fs) from a low-frequency sampling clock fs (10 kHz to 200 kHz) is challenging, while attempting to maintain low phase jitter. A traditional phase-lock loop (PLL) can do the frequency translation, but the added phase jitter prevents the generated system clock signal from effectively driving high-performance audio data converters. This applica
  • Troubleshooting I2C Bus Protocol
    PDF, 184 Kb, Archivo publicado: oct 19, 2009
    When using the I2Cв„ў bus protocol, the designer must ensure that the hardware complies with the I2C standard. This application report describes the I2C protocol and provides guidelines on debugging a missing acknowledgment, selecting the pullup resistors, or meeting the maximum capacitance load of an I2C bus. A conflict occurs if devices sharing the I2C bus have the same slave address. This

Linea modelo

Clasificación del fabricante

  • Semiconductors> Clock and Timing> Clock Generators> Spread-Spectrum Clocks