Datasheet Texas Instruments LMK61E0M-SIAR — Ficha de datos

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SNAS692A – JANUARY 2017 – REVISED MAY 2017 LMK61E0M Ultra-Low Jitter Programmable Oscillator With Internal EEPROM
1 Features 3 Description The LMK61E0 family of ultra-low jitter PLLatinumTM
programmable oscillators use fractional-N frequency
synthesizers with integrated VCOs to generate
commonly used reference clocks. The LMK61E0M
supports 3.3-V LVCMOS outputs. The device
features self start-up from on-chip EEPROM to
generate a factory programmed default output
frequency, or the device registers and EEPROM
settings are fully programmable in-system through I2C
serial interface. The device provides fine and coarse
frequency margining control through I2C serial
interface, making it a digitally-controlled oscillator
(DCXO). 1 Ultra-Low Noise, High Performance
– Jitter: 500-fs RMS Typical fOUT > 50 MHz on
LMK61E0M
LMK61E0M Supports 3.3-V LVCMOS Output up …