Datasheet Texas Instruments OMAP5912 — Ficha de datos

FabricanteTexas Instruments
SerieOMAP5912

Procesador de aplicaciones

Hojas de datos

OMAP5912 Applications Processor datasheet
PDF, 2.5 Mb, Revisión: E, Archivo publicado: dic 19, 2005

Precios

Estado

OMAP5912ZDYOMAP5912ZDYAOMAP5912ZZG
Estado del ciclo de vidaNRND (No recomendado para nuevos diseños)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)NRND (No recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNo

Embalaje

OMAP5912ZDYOMAP5912ZDYAOMAP5912ZZG
N123
Pin289289289
Package TypeZDYZDYZZG
Industry STD TermBGABGABGA MICROSTAR
JEDEC CodeS-PBGA-NS-PBGA-NS-PBGA-N
Package QTY84160
CarrierJEDEC TRAY (5+1)EIAJ TRAY (5+1)
Device MarkingOMAP5912OMAP5912ZZG
Width (mm)191912
Length (mm)191912
Thickness (mm)1.731.73.9
Pitch (mm)11.5
Max Height (mm)2.322.321.2
Mechanical DataDescargarDescargarDescargar

Plan ecológico

OMAP5912ZDYOMAP5912ZDYAOMAP5912ZZG
RoHSObedienteDesobedienteObediente
Pb gratisNo

Notas de aplicación

  • DSP Instruction Cache Performance on the OMAP5912
    PDF, 47 Kb, Archivo publicado: feb 28, 2005
  • Enabling high-speed USB OTG functionality on TI DSPs
    PDF, 191 Kb, Archivo publicado: mayo 18, 2007
  • OMAP591x: Tuning the System Memory Requirements of DSP/BIOS Link
    PDF, 251 Kb, Archivo publicado: marzo 16, 2005
    The DSP/BIOSв„ў Link software has been designed to implement inter-processor communication between a host device and a DSP. For the case of OMAP591x devices, the default configuration of the DSP/BIOS Link software requires that 2MB of system memory is reserved for exclusive use by DSP/BIOS Link. The intention was to provide developers using DSP/BIOS Link plenty of memory to begin with and enab
  • Programming the DSP MMU in the OMAP5910 Device
    PDF, 476 Kb, Archivo publicado: oct 7, 2004
    The OMAP5910 device from Texas Instruments (TI) has a new dual-core architecture that is optimized for multimedia applications in a low-power environment. It couples two processorsВ—a TI-enhanced TI925T general-purpose processor and an ultralow-power TMS320C55xв„ў (C55xв„ў) digital signal processor (DSP)В—with a rich set of peripherals and powerful interfaces to achieve optimal per
  • Using the CSL to complement OS dispatcher in handling Cascaded Interrupts
    PDF, 299 Kb, Archivo publicado: nov 8, 2004
    This application report discusses how CSL's INTC module could be used to share the task of dispatching interrupts with the OS, in scenarios where the OS's interrupt dispatcher does not comprehend cascaded interrupts.The solution involves having the CSL dispatch the cascaded interrupts alone, while completely leaving the job of dispatching primary CPU interrupts to the OS.We also discuss an
  • High-Speed Interface Layout Guidelines (Rev. G)
    PDF, 814 Kb, Revisión: G, Archivo publicado: jul 27, 2017
    As modern bus interface frequencies scale higher, care must be taken in the printed circuit board (PCB) layout phase of a design to ensure a robust solution.

Linea modelo

Clasificación del fabricante

  • Semiconductors> Processors> Other Processors