Datasheet Texas Instruments PLL1700 — Ficha de datos

PLL1700
PLL
170
0 В® 49%
FPO
SBOS096A – JANUARY 1998 – REVISED MAY 2007 MULTI-CLOCK GENERATOR
FEATURES DESCRIPTION в—Џ 27MHz MASTER CLOCK INPUT The PLL1700 is a low cost, multi-clock generator Phase
Lock Loop (PLL). в—Џ GENERATED AUDIO SYSTEM CLOCK:
SCKO1: 33.8688MHz (Fixed)
SCKO2: 256fS
SCKO3: 384fS
SCKO4: 768fS The PLL1700 can generate four systems clocks from a
27MHz reference input frequency.
The device gives customers both cost and space savings
by eliminating external components and enables customers to achieve the very low jitter performance needed for
high-performance audio digital-to-analog converters
(DACs) and/or analog-to-digital converters (ADCs). в—Џ ZERO PPM ERROR OUTPUT CLOCKS
в—Џ LOW CLOCK JITTER: 150ps at SCKO3
в—Џ MULTIPLE SAMPLING FREQUENCIES:
fS = 32kHz, 44.1kHz, 48kHz, 64kHz,
88.2kHz, 96kHz The PLL1700 is ideal for MPEG-2 applications that use a
27MHz master clock such as DVD players, DVD add-on
cards for multimedia PCs, digital HDTV systems, and settop boxes. в—Џ +3.3V CMOS LOGIC INTERFACE …