Datasheet Texas Instruments 5962-9951001QSA — Ficha de datos

FabricanteTexas Instruments
SerieSN54LVTH374
Numero de parte5962-9951001QSA
Datasheet Texas Instruments 5962-9951001QSA

Chanclas de tipo D activadas por borde octal con salidas de 3 estados 20-CFP -55 a 125

Hojas de datos

SN54LVTH374, SN74LVTH374 datasheet
PDF, 1.2 Mb, Revisión: H, Archivo publicado: oct 10, 2003
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin202020
Package TypeWWW
Industry STD TermCFPCFPCFP
JEDEC CodeR-GDFP-FR-GDFP-FR-GDFP-F
Package QTY111
CarrierTUBETUBETUBE
Device MarkingASNJ54LVTH374W5962-9951001QS
Width (mm)6.926.926.92
Length (mm)13.0913.0913.09
Thickness (mm)1.841.841.84
Pitch (mm)1.271.271.27
Max Height (mm)2.452.452.45
Mechanical DataDescargarDescargarDescargar

Paramétricos

3-State OutputYes
Bits8
F @ Nom Voltage(Max)160 Mhz
ICC @ Nom Voltage(Max)5 mA
Input TypeTTL
Operating Temperature Range-55 to 125 C
Output Drive (IOL/IOH)(Max)64/-32 mA
Output TypeTTL
Package GroupCFP
Package Size: mm2:W x LSee datasheet (CFP) PKG
RatingMilitary
Technology FamilyLVT
VCC(Max)3.6 V
VCC(Min)2.7 V
tpd @ Nom Voltage(Max)4.5 ns

Plan ecológico

RoHSSee ti.com

Notas de aplicación

  • Input and Output Characteristics of Digital Integrated Circuits
    PDF, 1.7 Mb, Archivo publicado: oct 1, 1996
    This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding the characteristics of the components. This knowledge is particularly useful when for example a decision must be made as to which circuit shou
  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Archivo publicado: dic 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, Archivo publicado: mayo 1, 1996
  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revisión: A, Archivo publicado: feb 6, 2015
  • TI IBIS File Creation Validation and Distribution Processes
    PDF, 380 Kb, Archivo publicado: agosto 29, 2002
    The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con
  • Live Insertion
    PDF, 150 Kb, Archivo publicado: oct 1, 1996
    Many applications require the ability to exchange modules in electronic systems without removing the supply voltage from the module (live insertion). For example an electronic telephone exchange must always remain operational even during module maintenance and repair. To avoid damaging components additional circuitry modifications are necessary. This document describes in detail the phenomena tha
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, Archivo publicado: mayo 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
  • Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
    PDF, 105 Kb, Revisión: A, Archivo publicado: agosto 1, 1997
    The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, Revisión: C, Archivo publicado: dic 2, 2015
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, Archivo publicado: jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revisión: B, Archivo publicado: mayo 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Introduction to Logic
    PDF, 93 Kb, Archivo publicado: abr 30, 2015
  • Implications of Slow or Floating CMOS Inputs (Rev. D)
    PDF, 260 Kb, Revisión: D, Archivo publicado: jun 23, 2016

Linea modelo

Serie: SN54LVTH374 (2)

Clasificación del fabricante

  • Semiconductors > Space & High Reliability > Logic Products > Flip-Flop/Latch/Registers

Otros nombres:

59629951001QSA, 5962 9951001QSA