Datasheet Texas Instruments SN65LVDS104PWR — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | SN65LVDS104 |
| Numero de parte | SN65LVDS104PWR |
Buffer de distribución de reloj LVDS 1: 4 16-TSSOP -40 a 85
Hojas de datos
SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters datasheet
PDF, 1.2 Mb, Revisión: G, Archivo publicado: dic 31, 2015
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 16 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | LVDS104 |
| Width (mm) | 4.4 |
| Length (mm) | 5 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Descargar |
Paramétricos
| Input Frequency(Max) | 400 MHz |
| Input Level | LVDS |
| Number of Outputs | 4 |
| Operating Temperature Range | -40 to 85 C |
| Output Frequency(Max) | 400 MHz |
| Output Level | LVDS |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG |
| Rating | Catalog |
| VCC | 3.3 V |
| VCC Out | 3.3 V |
Plan ecológico
| RoHS | Obediente |
Notas de aplicación
- DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CMLPDF, 135 Kb, Archivo publicado: feb 19, 2003
- AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)PDF, 417 Kb, Revisión: C, Archivo publicado: oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16
Linea modelo
Serie: SN65LVDS104 (8)
Clasificación del fabricante
- Semiconductors > Clock and Timing > Clock Buffers > Differential