Datasheet Texas Instruments SN74ALVCH162260DLR — Ficha de datos

FabricanteTexas Instruments
SerieSN74ALVCH162260
Numero de parteSN74ALVCH162260DLR
Datasheet Texas Instruments SN74ALVCH162260DLR

Pestillo de tipo D multiplexado de 12 a 24 bits con salidas de 3 estados 56-SSOP -40 a 85

Hojas de datos

SN74ALVCH162260 datasheet
PDF, 352 Kb, Revisión: I, Archivo publicado: agosto 5, 2004
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin56
Package TypeDL
Industry STD TermSSOP
JEDEC CodeR-PDSO-G
Package QTY1000
CarrierLARGE T&R
Device MarkingALVCH162260
Width (mm)7.49
Length (mm)18.41
Thickness (mm)2.59
Pitch (mm).635
Max Height (mm)2.79
Mechanical DataDescargar

Paramétricos

3-State OutputYes
Bits12
F @ Nom Voltage(Max)150 Mhz
ICC @ Nom Voltage(Max)0.04 mA
Operating Temperature Range-40 to 85 C
Output Drive (IOL/IOH)(Max)24/-24 mA
Package GroupSSOP
Package Size: mm2:W x L56SSOP: 191 mm2: 10.35 x 18.42(SSOP) PKG
RatingCatalog
Schmitt TriggerNo
Technology FamilyALVC
VCC(Max)3.6 V
VCC(Min)1.65 V
Voltage(Nom)1.8,2.5,2.7,3.3 V
tpd @ Nom Voltage(Max)5.9,5.8,4.9 ns

Plan ecológico

RoHSObediente

Notas de aplicación

  • TI SN74ALVC16835 Component Specification Analysis for PC100
    PDF, 43 Kb, Archivo publicado: agosto 3, 1998
    The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
  • Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
    PDF, 96 Kb, Revisión: A, Archivo publicado: mayo 13, 1998
    Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
  • Bus-Hold Circuit
    PDF, 418 Kb, Archivo publicado: feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revisión: B, Archivo publicado: mayo 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
    PDF, 154 Kb, Revisión: A, Archivo publicado: sept 8, 1999
    In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, Archivo publicado: mayo 1, 1996

Linea modelo

Clasificación del fabricante

  • Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Latch