Datasheet Texas Instruments SN74GTLP1394 — Ficha de datos

FabricanteTexas Instruments
SerieSN74GTLP1394
Datasheet Texas Instruments SN74GTLP1394

Bus Xcvr de velocidad de borde ajustable de LVTTL a GTLP de 2 bits con puerto LVTTL dividido, ruta de retroalimentación y polaridad seleccionable

Hojas de datos

SN74GTLP1394 datasheet
PDF, 882 Kb, Revisión: F, Archivo publicado: abr 25, 2003
Extracto del documento

Estado

SN74GTLP1394DSN74GTLP1394DRSN74GTLP1394PWSN74GTLP1394PWRSN74GTLP1394PWRE4
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNo

Embalaje

SN74GTLP1394DSN74GTLP1394DRSN74GTLP1394PWSN74GTLP1394PWRSN74GTLP1394PWRE4
N12345
Pin1616161616
Package TypeDDPWPWPW
Industry STD TermSOICSOICTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY4025009020002000
CarrierTUBELARGE T&RTUBELARGE T&RLARGE T&R
Device MarkingGTLP1394GTLP1394GP394GP394GP394
Width (mm)3.913.914.44.44.4
Length (mm)9.99.9555
Thickness (mm)1.581.58111
Pitch (mm)1.271.27.65.65.65
Max Height (mm)1.751.751.21.21.2
Mechanical DataDescargarDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsSN74GTLP1394D
SN74GTLP1394D
SN74GTLP1394DR
SN74GTLP1394DR
SN74GTLP1394PW
SN74GTLP1394PW
SN74GTLP1394PWR
SN74GTLP1394PWR
SN74GTLP1394PWRE4
SN74GTLP1394PWRE4
Bits22222
F @ Nom Voltage(Max), Mhz175175175175175
ICC @ Nom Voltage(Max), mA2020202020
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA100100100100100
Package GroupSOICSOICTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG16SOIC: 59 mm2: 6 x 9.9(SOIC)16SOIC: 59 mm2: 6 x 9.9(SOIC)16TSSOP: 32 mm2: 6.4 x 5(TSSOP)16TSSOP: 32 mm2: 6.4 x 5(TSSOP)16TSSOP: 32 mm2: 6.4 x 5(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNo
Technology FamilyGTLPGTLPGTLPGTLPGTLP
VCC(Max), V3.453.453.453.453.45
VCC(Min), V3.153.153.153.153.15
Voltage(Nom), V3.33.33.33.33.3
tpd @ Nom Voltage(Max), ns8.68.68.68.68.6

Plan ecológico

SN74GTLP1394DSN74GTLP1394DRSN74GTLP1394PWSN74GTLP1394PWRSN74GTLP1394PWRE4
RoHSObedienteObedienteObedienteObedienteObediente

Notas de aplicación

  • Texas Instruments GTLP Frequently Asked Questions
    PDF, 496 Kb, Archivo publicado: enero 1, 2001
    Using a question-and-answer format, advantages of TI?s GTLP devices, particularly for backplane applications, are presented, as well as differences between GTLP and GTL/LVDS devices. Applicable topics include data throughput rates, synchronous clocks, price and alternative sources, bus transceivers, live insertion, power consumption, backplane termination, voltage translation, IBIS and HSPICE mode
  • Logic in Live-Insertion Applications With a Focus on GTLP
    PDF, 493 Kb, Archivo publicado: enero 14, 2002
    Live-insertion capability is an essential part of today?s high-speed data systems because those systems are expected to run continuously without being powered down. This application report delves into the cause and prevention of live-insertion and nanosecond-discontinuity effects, using both simulation and actual test measurements from a specially built GTLP EVM. Hypothetical cases for precharge c
  • Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
    PDF, 585 Kb, Archivo publicado: abr 5, 2001
    This application report compares two approaches for synchronous bus-system designs. The focus of the report is the comparison of a system using central-synchronous system clock (CSSC) with a system operated with a source-synchronous system clock (SSSC).The basic characteristics of lines, key factors that influence the bus line delay, and the impedance of bus lines are described.The theoretical
  • Fast GTLP Backplanes With the GTLPH1655 (Rev. A)
    PDF, 1.1 Mb, Revisión: A, Archivo publicado: sept 19, 2000
    This revision of the Fast GTL Backplanes With the GTL1655 application report addresses improvements, such as the improved OECE circuitry and implementation of theTexas Instruments TI-OPCE circuitry, that have been incorporated in the GTLPH1655 device. These improvements significantly improve signal integrity in distributed loads.This application report describes the physical principles of fast
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, Archivo publicado: mayo 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

Linea modelo

Clasificación del fabricante

  • Semiconductors> Logic> Backplane Logic (GTL/TTL/BTL/ECL Transceiver/Translator)