SN74LVC32373A
32-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com SCES575 – JUNE 2004 – REVISED AUGUST 2005 FEATURES Member of the Texas Instruments Widebus+™
Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.2 ns at 3.3 V
Typical VOLP (Output Ground Bounce) 2 V at
VCC = 3.3 V, TA = 25В°C Ioff Supports Partial-Power-Down Mode
Operation
Supports Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION
This 32-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC32373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers. It can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the
latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are
latched at the levels set up at the D inputs. …
