Datasheet Texas Instruments SN74LVT182502 — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | SN74LVT182502 |
Dispositivos de prueba de escaneo ABT de 3.3 V con transceptores de bus universal de 18 bits
Hojas de datos
3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers (Rev. F)
PDF, 504 Kb, Revisión: F, Archivo publicado: jul 1, 1996
Estado
| SN74LVT182502PM | |
|---|---|
| Estado del ciclo de vida | Obsoleto (El fabricante ha interrumpido la producción del dispositivo) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| SN74LVT182502PM | |
|---|---|
| N | 1 |
| Pin | 64 |
| Package Type | PM |
| Industry STD Term | LQFP |
| JEDEC Code | S-PQFP-G |
| Width (mm) | 10 |
| Length (mm) | 10 |
| Thickness (mm) | 1.4 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.6 |
| Mechanical Data | Descargar |
Plan ecológico
| SN74LVT182502PM | |
|---|---|
| RoHS | Desobediente |
| Pb gratis | No |
Notas de aplicación
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, Archivo publicado: dic 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
Linea modelo
Serie: SN74LVT182502 (1)
Clasificación del fabricante
- Semiconductors> Logic> Specialty Logic> Boundary Scan (JTAG) Logic